Testing content addressable memories with physical fault models

Ma Lin; Yang Xu; Zhong Shiqiang; Chen Yunji

doi:10.1088/1674-4926/30/8/085001

J. Semicond. > 2009, Volume 30 > Issue 8 > 085001

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Testing content addressable memories with physical fault models

Ma Lin, Yang Xu, Zhong Shiqiang and Chen Yunji

+ Author Affiliations

DOI: 10.1088/1674-4926/30/8/085001

Abstract: Content addressable memory (CAM) is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N+2L+4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N+2L+5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms.

Key words: content addressable memory; test algorithm; physical fault model

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Ma Lin, Yang Xu, Zhong Shiqiang, Chen Yunji. Testing content addressable memories with physical fault models[J]. Journal of Semiconductors, 2009, 30(8): 085001. doi: 10.1088/1674-4926/30/8/085001

Ma L, Yang X, Zhong S Q, Chen Y J. Testing content addressable memories with physical fault models[J]. J. Semicond., 2009, 30(8): 085001. doi: 10.1088/1674-4926/30/8/085001.

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Received: 18 August 2015 Revised: 26 March 2009 Online: Published: 01 August 2009

Content addressable memory (CAM) is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N+2L+4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N+2L+5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms.

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