Abstract: A CMOS analog equalizer is designed to meet the different high speed communication specifications, such as USB 2.0, PCI-E and rapid IO. The proposed circuit architecture could facilitate the wide frequency scale ranging from 1 to 3.125 Gbps by adjusting the locations of pole and zero, so that the circuit can change its response accordingly as the channel characteristic alters. In order to balance the parasitic capacitors in the internal point, symmetric switches are addressed to generate the equal load for differential signals. A prototype chip was fabricated in 0.13-μm 1P8M mix-signal CMOS technology. The actual area is 0.49 × 0.5 mm², and the analog equalizer operates up to 3.125 Gbps over 3 m RG-58 coaxial cable and 50 cm FR4-PCB trace. The overall power dissipation is approximately 14.4 mW.

Key words: analog equalizer,  RG-58,  CMOS