| Citation: |
Lai Xinquan, Zeng Huali, Ye Qiang, He Huisen, Zhang Shasha, Sun Yuqing. Design of high efficiency dual-mode buck DC–DC converter[J]. Journal of Semiconductors, 2010, 31(11): 115005. doi: 10.1088/1674-4926/31/11/115005
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Lai X Q, Zeng H L, Ye Q, He H S, Zhang S S, Sun Y Q. Design of high efficiency dual-mode buck DC–DC converter[J]. J. Semicond., 2010, 31(11): 115005. doi: 10.1088/1674-4926/31/11/115005.
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Abstract
A buck DC–DC switching regulator with high efficiency is implemented by automatically altering the modulation mode according to load current, and it can operate with an input range of 4.5 to 30 V. At light load current, the converter operates in skip mode. The converter enters PWM mode operation with increasing load current. It reduces the switching loss at light load and standby state, which results in prolonging battery lifetime and stand-by time. Meanwhile, externally adjustable soft-start minimizes the inrush supply current and avoids the overshoot of output voltage at initial startup. The regulator is fabricated by a 0.6 μm CDMOS process. The test results show that, under the condition of 3.3 V output, the efficiency is up to 64% at 5 mA and the maximum efficiency is 95.5%.-
Keywords:
- high efficiency
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References
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Proportional views
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