| Citation: |
Xiao Shimao, Yu Yunfeng, Ma Chengyan, Ye Tianchun, Yin Ming. A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver[J]. Journal of Semiconductors, 2010, 31(3): 035004. doi: 10.1088/1674-4926/31/3/035004
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Xiao S M, Yu Y F, Ma C Y, Ye T C, Yin M. A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver[J]. J. Semicond., 2010, 31(3): 035004. doi: 10.1088/1674-4926/31/3/035004.
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A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver
DOI: 10.1088/1674-4926/31/3/035004
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Abstract
The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than –95 dBc at 200 kHz offset while the measured tuning range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.-
Keywords:
- CMOS
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References
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Proportional views
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