SEMICONDUCTOR INTEGRATED CIRCUITS
Luo Hao, Han Yan, Ray C. C. Cheung, Han Xiaoxia, Ma Shaoyu, Ying Peng and Zhu Dazhong
Abstract: A high-performance low-power ΣΔ analog-to-digital converter (ADC) for digital audio applications isdescribed. It consists of a 2-1 cascaded ΣΔ modulator and a decimation filter. Various design optimizations are implemented in the system design, circuit implementation and layout design, including a high-overload-level coefficient-optimized modulator architecture, a power-efficient class A/AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm2, which dissipates only 2.1 mA quiescent current in the analog circuits.
Key words: ΣΔ?? modulator, decimation filter, low power, audio analog-to-digital converter
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Received: 18 August 2015 Revised: 11 December 2009 Online: Published: 01 May 2010
| Citation: |
Luo Hao, Han Yan, Ray C. C. Cheung, Han Xiaoxia, Ma Shaoyu, Ying Peng, Zhu Dazhong. A high-performance, low-power ΣΔ ADC for digital audio applications[J]. Journal of Semiconductors, 2010, 31(5): 055009. doi: 10.1088/1674-4926/31/5/055009
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Luo H, Han Y, R C C Cheung, Han X X, Ma S Y, Ying P, Zhu D Z. A high-performance, low-power ΣΔ ADC for digital audio applications[J]. J. Semicond., 2010, 31(5): 055009. doi: 10.1088/1674-4926/31/5/055009.
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