A 2-GS/s 6-bit self-calibrated flash ADC

Zhang Youtao; Li Xiaopeng; Zhang Min; Liu Ao; Chen Chen

doi:10.1088/1674-4926/31/9/095013

J. Semicond. > 2010, Volume 31 > Issue 9 > 095013

SEMICONDUCTOR INTEGRATED CIRCUITS

A 2-GS/s 6-bit self-calibrated flash ADC

Zhang Youtao, Li Xiaopeng, Zhang Min, Liu Ao and Chen Chen

+ Author Affiliations

DOI: 10.1088/1674-4926/31/9/095013

Abstract: A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μm CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.

Key words: analog-to-digital conversion

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Zhang Youtao, Li Xiaopeng, Zhang Min, Liu Ao, Chen Chen. A 2-GS/s 6-bit self-calibrated flash ADC[J]. Journal of Semiconductors, 2010, 31(9): 095013. doi: 10.1088/1674-4926/31/9/095013

Zhang Y T, Li X P, Zhang M, Liu A, Chen C. A 2-GS/s 6-bit self-calibrated flash ADC[J]. J. Semicond., 2010, 31(9): 095013. doi: 10.1088/1674-4926/31/9/095013.

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Received: 18 August 2015 Revised: Online: Published: 01 September 2010

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μm CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.

A 2-GS/s 6-bit self-calibrated flash ADC

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