
SEMICONDUCTOR INTEGRATED CIRCUITS
Abstract: A digitally controlled oscillator (DCO) using a three-transistor XOR gate as the variable load has been presented. A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-, five- and seven-stage DCO circuits have been designed using the proposed delay cell. The output frequency is controlled digitally with bits applied to the delay cells. The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW, respectively, with a change in the control word 111-000. The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW, respectively, with a change in the control word 11111-00000. Moreover, the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW, respectively, with a varying control word 1111111-0000000. The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.
Key words: digital control oscillator, delay cell, power consumption, variable capacitance, voltage controlled oscillators, XOR gate
[1] | |
[2] | |
[3] | |
[4] | |
[5] | |
[6] | |
[7] | |
[8] | |
[9] | |
[10] | |
[11] | |
[12] | |
[13] | |
[14] | |
[15] | |
[16] | |
[17] | |
[18] | |
[19] | |
[20] | |
[21] |
1 |
Raheela Rasool, Najeeb-ud-Din, G. M. Rather Journal of Semiconductors, 2019, 40(12): 122401. doi: 10.1088/1674-4926/40/12/122401 |
2 |
Large area perovskite solar cell module Longhua Cai, Lusheng Liang, Jifeng Wu, Bin Ding, Lili Gao, et al. Journal of Semiconductors, 2017, 38(1): 014006. doi: 10.1088/1674-4926/38/1/014006 |
3 |
A monolithic integrated low-voltage deep brain stimulator with wireless power and data transmission Zhang Zhang, Ye Tan, Jianmin Zeng, Xu Han, Xin Cheng, et al. Journal of Semiconductors, 2016, 37(9): 095003. doi: 10.1088/1674-4926/37/9/095003 |
4 |
Analytical modeling and simulation of germanium single gate silicon on insulator TFET T. S. Arun Samuel, N. B. Balamurugan Journal of Semiconductors, 2014, 35(3): 034002. doi: 10.1088/1674-4926/35/3/034002 |
5 |
Binbin Jie, Chihtang Sah Journal of Semiconductors, 2014, 35(2): 021001. doi: 10.1088/1674-4926/35/2/021001 |
6 |
A trench accumulation layer controlled insulated gate bipolar transistor with a semi-SJ structure Binghua Li, Frank X. C. Jiang, Zhigui Li, Xinnan Lin Journal of Semiconductors, 2013, 34(12): 124001. doi: 10.1088/1674-4926/34/12/124001 |
7 |
Capacitance-voltage analysis of a high-k dielectric on silicon Davinder Rathee, Sandeep K. Arya, Mukesh Kumar Journal of Semiconductors, 2012, 33(2): 022001. doi: 10.1088/1674-4926/33/2/022001 |
8 |
Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate Manoj Kumar, Sandeep K. Arya, Sujata Pandey Journal of Semiconductors, 2012, 33(3): 035001. doi: 10.1088/1674-4926/33/3/035001 |
9 |
Wang Yongshun, Feng Jingjing, Liu Chunjuan, Wang Zaixing, Zhang Caizhen, et al. Journal of Semiconductors, 2011, 32(11): 114005. doi: 10.1088/1674-4926/32/11/114005 |
10 |
MOS Capacitance–Voltage Characteristics from Electron-Trapping at Dopant Donor Impurity Jie Binbin, Sah Chihtang Journal of Semiconductors, 2011, 32(4): 041001. doi: 10.1088/1674-4926/32/4/041001 |
11 |
Ali Ahaitouf, Abdelaziz Ahaitouf, Jean Paul Salvestrini, Hussein Srour Journal of Semiconductors, 2011, 32(10): 104002. doi: 10.1088/1674-4926/32/10/104002 |
12 |
Amit Chaudhry, J. N. Roy Journal of Semiconductors, 2010, 31(11): 114001. doi: 10.1088/1674-4926/31/11/114001 |
13 |
A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank Tian Huanhuan, Li Zhiqiang, Chen Pufeng, Wu Rufei, Zhang Haiying, et al. Journal of Semiconductors, 2010, 31(12): 125003. doi: 10.1088/1674-4926/31/12/125003 |
14 |
Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance Dong Yaoqi, Kong Weiran, Nhan Do, Wang Shiuh-Luen, Lee Gabriel, et al. Journal of Semiconductors, 2010, 31(6): 064012. doi: 10.1088/1674-4926/31/6/064012 |
15 |
Capacitance–voltage characterization of fully silicided gated MOS capacitor Wang Baomin, Ru Guoping, Jiang Yulong, Qu Xinping, Li Bingzong, et al. Journal of Semiconductors, 2009, 30(3): 034002. doi: 10.1088/1674-4926/30/3/034002 |
16 |
A Simulation of the Capacitance-Voltage Characteristics of a Ge/Si Quantum-Well Structure Cheng Peihong, Huang Shihua Journal of Semiconductors, 2008, 29(1): 110-115. |
17 |
Relation of Negative Capacitance in LED to Rotational Frequency Tan Yanliang, You Kaiming, Chen Liezun, Yuan Hongzhi Chinese Journal of Semiconductors , 2007, 28(5): 741-744. |
18 |
Elmore Delay Estimation of Two Adjacent Coupling Interconnects Dong Gang, Yang Yintang, Li Yuejin Chinese Journal of Semiconductors , 2006, 27(1): 54-58. |
19 |
Simulation of a Double-Gate Dynamic Threshold Voltage Fully Depleted Silicon-on-Insulator nMOSFET Bi Jinshun, Wu Junfeng, Hai Chaohe Chinese Journal of Semiconductors , 2006, 27(1): 35-40. |
20 |
Tang Lu, Wang Zhigong, Huang Ting, Li Zhiqun Chinese Journal of Semiconductors , 2006, 27(3): 459-466. |
Article views: 3724 Times PDF downloads: 3673 Times Cited by: 0 Times
Received: 03 December 2014 Revised: 09 June 2011 Online: Published: 01 October 2011
Citation: |
Manoj Kumar, Sandeep K. Arya, Sujata Pandey. Digitally controlled oscillator design with a variable capacitance XOR gate[J]. Journal of Semiconductors, 2011, 32(10): 105001. doi: 10.1088/1674-4926/32/10/105001
****
M Kumar, S K Arya, S Pandey. Digitally controlled oscillator design with a variable capacitance XOR gate[J]. J. Semicond., 2011, 32(10): 105001. doi: 10.1088/1674-4926/32/10/105001.
|
[1] | |
[2] | |
[3] | |
[4] | |
[5] | |
[6] | |
[7] | |
[8] | |
[9] | |
[10] | |
[11] | |
[12] | |
[13] | |
[14] | |
[15] | |
[16] | |
[17] | |
[18] | |
[19] | |
[20] | |
[21] |
Journal of Semiconductors © 2017 All Rights Reserved 京ICP备05085259号-2