A cryogenic SAR ADC for infrared readout circuits

Zhao Hongliang; Zhao Yiqiang; Zhang Zhisheng

doi:10.1088/1674-4926/32/11/115015

J. Semicond. > 2011, Volume 32 > Issue 11 > 115015

SEMICONDUCTOR INTEGRATED CIRCUITS

A cryogenic SAR ADC for infrared readout circuits

Zhao Hongliang, Zhao Yiqiang and Zhang Zhisheng

+ Author Affiliations

DOI: 10.1088/1674-4926/32/11/115015

Abstract: A cryogenic successive approximation register (SAR) analog to digital converter (ADC) is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit's performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature (from room temperature down to 77 K) operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity (DNL) and 0.59 LSB maximum integral nonlinearity (INL). It achieves 9.3 bit effective number of bits (ENOB) with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm².

Key words: cryogenic ADC

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Zhao Hongliang, Zhao Yiqiang, Zhang Zhisheng. A cryogenic SAR ADC for infrared readout circuits[J]. Journal of Semiconductors, 2011, 32(11): 115015. doi: 10.1088/1674-4926/32/11/115015

Zhao H L, Zhao Y Q, Zhang Z S. A cryogenic SAR ADC for infrared readout circuits[J]. J. Semicond., 2011, 32(11): 115015. doi: 10.1088/1674-4926/32/11/115015.

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Received: 20 August 2015 Revised: 27 May 2011 Online: Published: 01 November 2011

A cryogenic successive approximation register (SAR) analog to digital converter (ADC) is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit's performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature (from room temperature down to 77 K) operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity (DNL) and 0.59 LSB maximum integral nonlinearity (INL). It achieves 9.3 bit effective number of bits (ENOB) with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm².

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