A novel high-voltage device structure with an N<sup>+</sup> ring in substrate and the breakdown voltage model

Li Qi; Zhu Jinluan; Wang Weidong; Yue Hongwei; Jin Liangnian

doi:10.1088/1674-4926/32/12/124005

J. Semicond. > 2011, Volume 32 > Issue 12 > 124005

SEMICONDUCTOR DEVICES

A novel high-voltage device structure with an N⁺ ring in substrate and the breakdown voltage model

Li Qi, Zhu Jinluan, Wang Weidong, Yue Hongwei and Jin Liangnian

+ Author Affiliations

DOI: 10.1088/1674-4926/32/12/124005

Abstract: A novel high-voltage device structure with a floating heavily doped N⁺ ring embedded in the substrate is reported, which is called FR LDMOS. When the N⁺ ring is introduced in the device substrate, the electric field peak of the main junction is reduced due to the transfer of the voltage from the main junction to the N⁺ ring junction, and the vertical breakdown characteristic is improved significantly. Based on the Poisson equation of cylindrical coordinates, a breakdown voltage model is developed. The numerical results indicate that the breakdown voltage of the proposed device is increased by 56% in comparison to conventional LDMOS.

Key words: floating ring, model, breakdown voltage, modulation

[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]

1	Source-field-plated Ga₂O₃ MOSFET with a breakdown voltage of 550 V Yuanjie Lü, Xubo Song, Zezhao He, Yuangang Wang, Xin Tan, et al. Journal of Semiconductors, 2019, 40(1): 012803. doi: 10.1088/1674-4926/40/1/012803
2	Modeling on oxide dependent 2DEG sheet charge density and threshold voltage in AlGaN/GaN MOSHEMT J. Panda, K. Jena, R. Swain, T. R. Lenka Journal of Semiconductors, 2016, 37(4): 044003. doi: 10.1088/1674-4926/37/4/044003
3	A transient-enhanced NMOS low dropout voltage regulator with parallel feedback compensation Han Wang, Lin Tan Journal of Semiconductors, 2016, 37(2): 025005. doi: 10.1088/1674-4926/37/2/025005
4	A monolithic integrated low-voltage deep brain stimulator with wireless power and data transmission Zhang Zhang, Ye Tan, Jianmin Zeng, Xu Han, Xin Cheng, et al. Journal of Semiconductors, 2016, 37(9): 095003. doi: 10.1088/1674-4926/37/9/095003
5	Model development for analyzing 2DEG sheet charge density and threshold voltage considering interface DOS for AlInN/GaN MOSHEMT Devashish Pandey, T.R. Lenka Journal of Semiconductors, 2014, 35(10): 104001. doi: 10.1088/1674-4926/35/10/104001
6	Simulating and modeling the breakdown voltage in a semi-insulating GaAs P⁺N junction diode A. Resfa, Brahimi.R. Menezla, M. Benchhima Journal of Semiconductors, 2014, 35(8): 084002. doi: 10.1088/1674-4926/35/8/084002
7	An analytical model for the drain-source breakdown voltage of RF LDMOS power transistors with a Faraday shield Zhang Wenmin, Zhang Wei, Fu Jun, Wang Yudong Journal of Semiconductors, 2012, 33(4): 044001. doi: 10.1088/1674-4926/33/4/044001
8	A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs Wang Honglai, Zhang Xiaoxing, Dai Yujie, Lü Yingjie, Toshimasa Matsuoka, et al. Journal of Semiconductors, 2011, 32(8): 085009. doi: 10.1088/1674-4926/32/8/085009
9	Silicide-block-film effects on high voltage drain-extended MOS transistors Wang Lei, Gao Chao, Liu Bo, Hu Jian, Lee Po, et al. Journal of Semiconductors, 2009, 30(3): 034003. doi: 10.1088/1674-4926/30/3/034003
10	Modeling of High-Voltage LDMOS for PDP Driver ICs Li Haisong, Sun Weifeng, Yi Yangbo, Shi Longxing Journal of Semiconductors, 2008, 29(11): 2110-2114.
11	Analytical Model and Optimization of Bulk-Silicon Surface Implanted LDMOS with p Buried Layer Li Qi, Zhang Bo, Li Zhaoji Chinese Journal of Semiconductors , 2007, 28(8): 1267-1271.
12	2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs Ji Feng, Xu Jingping, Lai P T, Chen Weibing, Li Yanping, et al. Chinese Journal of Semiconductors , 2006, 27(10): 1725-1731.
13	A Novel Offset-Cancellation Technique for Low Voltage CMOS Differential Amplifiers Han Shuguang, Chi Baoyong, Wang Zhihua Chinese Journal of Semiconductors , 2006, 27(5): 778-782.
14	Low Voltage Flash Memory Cells Using SiGe Quantum Dots for Enhancing F-N Tunneling Deng Ning, Pan Liyang, Liu Zhihong, Zhu Jun, Chen Peiyi, et al. Chinese Journal of Semiconductors , 2006, 27(3): 454-458.
15	Analytical Model for the Electric Field Distribution of an SOI High Voltage Device with a Compound Dielectric Layer Luo Xiaorong, Li Zhaoji, Zhang Bo Chinese Journal of Semiconductors , 2006, 27(11): 2005-2010.
16	Breakdown Voltage and Charge to Breakdown Investigation of Gate Oxide of 0.18μm Dual Gate CMOS Process with Different Measurement Methods Zhao Yi, Wan Xinggong, Xu Xiangming, Cao Gang, Bu Jiao, et al. Chinese Journal of Semiconductors , 2006, 27(2): 290-293.
17	Breakdown Characteristics of SOI LDMOS High VoltageDevices with Variable Low k Dielectric Layer Luo Xiaorong, 李肇基, Li Zhaoji Chinese Journal of Semiconductors , 2006, 27(5): 881-885.
18	An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs Li Ruizhen, Han Zhengsheng Chinese Journal of Semiconductors , 2005, 26(12): 2303-2308.
19	A Breakdown Model of Thin Drift Region LDMOS with a Step Doping Profile Li Qi, Zhang Bo, Li Zhaoji Chinese Journal of Semiconductors , 2005, 26(11): 2159-2163.
20	On-State Breakdown Model for High Voltage RESURF LDMOS Fang Jian, Yi Kun, Li Zhaoji, and Zhang Bo（436） Chinese Journal of Semiconductors , 2005, 26(3): 436-442.

Search

GET CITATION

Li Qi, Zhu Jinluan, Wang Weidong, Yue Hongwei, Jin Liangnian. A novel high-voltage device structure with an N⁺ ring in substrate and the breakdown voltage model[J]. Journal of Semiconductors, 2011, 32(12): 124005. doi: 10.1088/1674-4926/32/12/124005

Li Q, Zhu J L, Wang W D, Yue H W, Jin L N. A novel high-voltage device structure with an N+ ring in substrate and the breakdown voltage model[J]. J. Semicond., 2011, 32(12): 124005. doi: 10.1088/1674-4926/32/12/124005.

Export: BibTex EndNote

Article Metrics

Article views: 3929 Times PDF downloads: 2094 Times Cited by: 0 Times

History

Received: 20 August 2015 Revised: 07 August 2011 Online: Published: 01 December 2011

A novel high-voltage device structure with a floating heavily doped N⁺ ring embedded in the substrate is reported, which is called FR LDMOS. When the N⁺ ring is introduced in the device substrate, the electric field peak of the main junction is reduced due to the transfer of the voltage from the main junction to the N⁺ ring junction, and the vertical breakdown characteristic is improved significantly. Based on the Poisson equation of cylindrical coordinates, a breakdown voltage model is developed. The numerical results indicate that the breakdown voltage of the proposed device is increased by 56% in comparison to conventional LDMOS.

A novel high-voltage device structure with an N⁺ ring in substrate and the breakdown voltage model

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

A novel high-voltage device structure with an N⁺ ring in substrate and the breakdown voltage model

DOI: 10.1088/1674-4926/32/12/124005

Abstract

References

Proportional views

Catalog

A novel high-voltage device structure with an N+ ring in substrate and the breakdown voltage model

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

A novel high-voltage device structure with an N+ ring in substrate and the breakdown voltage model

DOI: 10.1088/1674-4926/32/12/124005

Abstract

References

Proportional views

Catalog

Export File

Citation

Format

Content

A novel high-voltage device structure with an N⁺ ring in substrate and the breakdown voltage model

A novel high-voltage device structure with an N⁺ ring in substrate and the breakdown voltage model