A new shallow trench and planar gate MOSFET structure based on VDMOS technology

Wang Cailin; Sun Cheng

doi:10.1088/1674-4926/32/2/024007

J. Semicond. > 2011, Volume 32 > Issue 2 > 024007

SEMICONDUCTOR DEVICES

A new shallow trench and planar gate MOSFET structure based on VDMOS technology

Wang Cailin and Sun Cheng

+ Author Affiliations

DOI: 10.1088/1674-4926/32/2/024007

Abstract: This paper proposes a new shallow trench and planar gate MOSFET (TPMOS) structure based on VDMOS technology, in which the shallow trench is located at the center of the n^- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.

Key words: power MOSFET

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Received: 18 August 2015 Revised: 20 September 2010 Online: Published: 01 February 2011

This paper proposes a new shallow trench and planar gate MOSFET (TPMOS) structure based on VDMOS technology, in which the shallow trench is located at the center of the n^- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.

A new shallow trench and planar gate MOSFET structure based on VDMOS technology

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A new shallow trench and planar gate MOSFET structure based on VDMOS technology

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