Abstract: A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18 μ m CMOS technology. A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance. A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature (I/Q) local oscillating signal. A high-speed 8/9 dual-modulus prescaler (DMP), a programmable-delay phase frequency detector without dead-zone problem, and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz, and the phase noise is –98.53 dBc/Hz at 100-kHz offset and –121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply. The total area of the receiver is 2.4 × 1.6 mm².

Key words: Beidou receiver, frequency synthesizer, voltage-controlled oscillator, quadrature output divider, phase noise