| Citation: |
Fan Xue, Li Ping, Li Wei, Zhang Bin, Xie Xiaodong, Wang Gang, Hu Bin, Zhai Yahong. Gate-enclosed NMOS transistors[J]. Journal of Semiconductors, 2011, 32(8): 084002. doi: 10.1088/1674-4926/32/8/084002
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Fan X, Li P, Li W, Zhang B, Xie X D, Wang G, Hu B, Zhai Y H. Gate-enclosed NMOS transistors[J]. J. Semicond., 2011, 32(8): 084002. doi: 10.1088/1674-4926/32/8/084002.
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Abstract
In order to quantitatively compare the design cost and performance of various gate styles, NMOS transistors with two-edged, annular and ring gate layouts were designed and fabricated by a commercial 0.35 μm CMOS process. By comparing the minimum W/L ratios and transistor areas, it was found that either the annular layout or its ring counterpart incurs a higher area penalty that depends on the W/L ratio of the transistor to be designed. Furthermore, by comparing the output and transfer characteristics of the transistors and analyzing the popular existing methods for extracting the effective W/L ratio, it was shown that the mid-line approximation for annular NMOS could incur an error of more than 10%. It was also demonstrated that the foundry-provided extraction tool needs significant adaptation when being applied to the enclosed-gate transistors, since it is targeted only toward the two-edged transistor. A simple approach for rough extraction of the W/L ratio for the ring-gate NMOS was presented and its effectiveness was confirmed by the experimental results with an error up to 8%.-
Keywords:
- radiation
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] -
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