Abstract: A new design technique for merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) is presented. For reducing the aperture error in the first stage of the pipelined ADC, a symmetrical structure is used in a flash ADC and MDAC. Furthermore, a variable resistor tuning network is placed at the flash input to compensate for different cutoff frequencies of the input impedances of the flash and MDAC. The circuit also has a clear clock phase in the MDAC and separate sampling capacitors in the flash ADC to eliminate the nonlinear charge kickback to the input signal. The proposed circuit, designed using ASMC 0.35-μm BiCMOS technology, occupies an area of 1.4 × 9 mm² and is used as the front-end stage in a 14-bit 125-MS/s pipelined ADC. After the trim circuit is enabled, the measured signal-to-noise ratio is improved from 71.5 to 73.6 dB and the spurious free dynamic range is improved from 80.5 to 83.1 dB with a 30.8 MHz input. The maximum input frequency is up to 150 MHz without steep performance degradations.

Key words: pipelined analog-to-digital converter, sample-and-hold amplifier, SHA-less, aperture error