Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

Manoj Kumar; Sandeep K. Arya; Sujata Pandey

doi:10.1088/1674-4926/33/3/035001

J. Semicond. > 2012, Volume 33 > Issue 3 > 035001

SEMICONDUCTOR INTEGRATED CIRCUITS

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

Manoj Kumar, Sandeep K. Arya and Sujata Pandey

+ Author Affiliations

DOI: 10.1088/1674-4926/33/3/035001

Abstract: Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

Key words: digital control oscillator, delay cell, power consumption, voltage controlled oscillators

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Manoj Kumar, Sandeep K. Arya, Sujata Pandey. Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate[J]. Journal of Semiconductors, 2012, 33(3): 035001. doi: 10.1088/1674-4926/33/3/035001

M Kumar, S K Arya, S Pandey. Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate[J]. J. Semicond., 2012, 33(3): 035001. doi: 10.1088/1674-4926/33/3/035001.

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Received: 03 December 2014 Revised: 24 October 2011 Online: Published: 01 March 2012

Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

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Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

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