| Citation: |
Hu Xiarong, Zhang Bo, Luo Xiaorong, Li Zhaoji. Universal trench design method for a high-voltage SOI trench LDMOS[J]. Journal of Semiconductors, 2012, 33(7): 074006. doi: 10.1088/1674-4926/33/7/074006
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Hu X R, Zhang B, Luo X R, Li Z J. Universal trench design method for a high-voltage SOI trench LDMOS[J]. J. Semicond., 2012, 33(7): 074006. doi: 10.1088/1674-4926/33/7/074006.
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Universal trench design method for a high-voltage SOI trench LDMOS
DOI: 10.1088/1674-4926/33/7/074006
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Abstract
The design method for a high-voltage SOI trench LDMOS for various trench permittivities, widths and depths is introduced. A universal method for efficient design is presented for the first time, taking the trade-off between breakdown voltage (BV) and specific on-resistance (Rs,on) into account. The high-k (relative permittivity) dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench. An SOI LDMOS with a vacuum trench in the drift region is also discussed. Simulation results show that the high FOM BV2/Rs,on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.-
Keywords:
- SOI,
- trench,
- permittivity,
- RESURF,
- LDMOS,
- breakdown voltage
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] -
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