J. Semicond. > 2012, Volume 33 > Issue 8 > 085002

SEMICONDUCTOR INTEGRATED CIRCUITS

An SEU-hardened latch with a triple-interlocked structure

Li Yuanqing, Yao Suying, Xu Jiangtao and Gao Jing

+ Author Affiliations
DOI: 10.1088/1674-4926/33/8/085002

PDF

Abstract: A single event upset (SEU) tolerant latch with a triple-interlocked structure is presented. Its self-recovery mechanism is implemented by using three pairs of guard-gates and inverters to construct feedback lines inside the structure. This latch effectively suppresses the effects of charge deposition at any single internal node caused by particle strikes. Three recently reported SEU-hardened latches are chosen and compared with this latch in terms of reliability. The potential problems that these three latches could still get flipped due to single event effects or single event effects plus crosstalk coupling are pointed out, which can be mitigated by this proposed latch. The SEU tolerance of each latch design is evaluated through circuit-level SEU injection simulation. Furthermore, discussions on the crosstalk robustness and some other characteristics of these latches are also presented.

Key words: single event upsetsingle event transientlatchtriple-interlockedfault injectioncrosstalk

[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
  • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 4058 Times PDF downloads: 2291 Times Cited by: 0 Times

    History

    Received: 20 August 2015 Revised: 16 March 2012 Online: Published: 01 August 2012

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Li Yuanqing, Yao Suying, Xu Jiangtao, Gao Jing. An SEU-hardened latch with a triple-interlocked structure[J]. Journal of Semiconductors, 2012, 33(8): 085002. doi: 10.1088/1674-4926/33/8/085002 ****Li Y Q, Yao S Y, Xu J T, Gao J. An SEU-hardened latch with a triple-interlocked structure[J]. J. Semicond., 2012, 33(8): 085002. doi: 10.1088/1674-4926/33/8/085002.
      Citation:
      Li Yuanqing, Yao Suying, Xu Jiangtao, Gao Jing. An SEU-hardened latch with a triple-interlocked structure[J]. Journal of Semiconductors, 2012, 33(8): 085002. doi: 10.1088/1674-4926/33/8/085002 ****
      Li Y Q, Yao S Y, Xu J T, Gao J. An SEU-hardened latch with a triple-interlocked structure[J]. J. Semicond., 2012, 33(8): 085002. doi: 10.1088/1674-4926/33/8/085002.

      An SEU-hardened latch with a triple-interlocked structure

      DOI: 10.1088/1674-4926/33/8/085002
      Funds:

      The National Natural Science Foundation of China (General Program, Key Program, Major Research Plan)

      • Received Date: 2015-08-20
      • Accepted Date: 2012-01-16
      • Revised Date: 2012-03-16
      • Published Date: 2012-07-27

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return