J. Semicond. > 2012, Volume 33 > Issue 8 > 086001

SEMICONDUCTOR TECHNOLOGY

Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits

Ruan Wenbiao, Chen Lan, Ma Tianyu, Fang Jingjing, Zhang He and Ye Tianchun

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DOI: 10.1088/1674-4926/33/8/086001

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Abstract: A copper chemical mechanical polishing (Cu CMP) process is reviewed and analyzed from the view of chemical physics. Three steps Cu CMP process modeling is set up based on the actual process of manufacturing and pattern-density-step-height (PDSH) modeling from MIT. To catch the pattern dependency, a 65 nm testing chip is designed and processed in the foundry. Following the model parameter extraction procedure, the model parameters are extracted and verified by testing data from the 65 nm testing chip. A comparison of results between the model predictions and test data show that the former has the same trend as the latter and the largest deviation is less than 5 nm. Third party testing data gives further evidence to support the great performance of model parameter optimization. Since precise CMP process modeling is used for the design of manufacturability (DFM) checks, critical hotspots are displayed and eliminated, which will assure good yield and production capacity of IC.

Key words: chemical mechanical polishing

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    Received: 20 August 2015 Revised: 09 April 2012 Online: Published: 01 August 2012

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      Ruan Wenbiao, Chen Lan, Ma Tianyu, Fang Jingjing, Zhang He, Ye Tianchun. Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits[J]. Journal of Semiconductors, 2012, 33(8): 086001. doi: 10.1088/1674-4926/33/8/086001 ****Ruan W B, Chen L, Ma T Y, Fang J J, Zhang H, Ye T C. Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits[J]. J. Semicond., 2012, 33(8): 086001. doi: 10.1088/1674-4926/33/8/086001.
      Citation:
      Ruan Wenbiao, Chen Lan, Ma Tianyu, Fang Jingjing, Zhang He, Ye Tianchun. Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits[J]. Journal of Semiconductors, 2012, 33(8): 086001. doi: 10.1088/1674-4926/33/8/086001 ****
      Ruan W B, Chen L, Ma T Y, Fang J J, Zhang H, Ye T C. Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits[J]. J. Semicond., 2012, 33(8): 086001. doi: 10.1088/1674-4926/33/8/086001.

      Optimization of a Cu CMP process modeling parameters of nanometer integrated circuits

      DOI: 10.1088/1674-4926/33/8/086001
      • Received Date: 2015-08-20
      • Accepted Date: 2012-02-02
      • Revised Date: 2012-04-09
      • Published Date: 2012-07-27

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