A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

Qiao Ning; Zhang Guoquan; Yang Bo; Liu Zhongli; Yu Fang

doi:10.1088/1674-4926/33/9/095005

J. Semicond. > 2012, Volume 33 > Issue 9 > 095005

SEMICONDUCTOR INTEGRATED CIRCUITS

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

Qiao Ning, Zhang Guoquan, Yang Bo, Liu Zhongli and Yu Fang

+ Author Affiliations

DOI: 10.1088/1674-4926/33/9/095005

Abstract: A 10-bit 50-MS/s reference-free low power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC (CDAC) is implemented to cancel the offset of the latch-type sense amplifier (SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit (FOM) of 61.1 fJ/conversion-step.

Key words: successive approximation register, analog-to-digital converter, reference-free, on-chip calibration, energy efficient

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Qiao Ning, Zhang Guoquan, Yang Bo, Liu Zhongli, Yu Fang. A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology[J]. Journal of Semiconductors, 2012, 33(9): 095005. doi: 10.1088/1674-4926/33/9/095005

Qiao N, Zhang G Q, Yang B, Liu Z L, Yu F. A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology[J]. J. Semicond., 2012, 33(9): 095005. doi: 10.1088/1674-4926/33/9/095005.

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Received: 20 August 2015 Revised: 10 April 2012 Online: Published: 01 September 2012

A 10-bit 50-MS/s reference-free low power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC (CDAC) is implemented to cancel the offset of the latch-type sense amplifier (SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit (FOM) of 61.1 fJ/conversion-step.

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

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