Fig. 1.
Current steering DAC with an $R$ -2$R$ structure.
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| Citation: |
Lei Zhou, Danyu Wu, Fan Jiang, Zhi Jin, Xinyu Liu. A 10 Gsps 8 bit digital-to-analog converter with a built-in self-test circuit[J]. Journal of Semiconductors, 2013, 34(12): 125007. doi: 10.1088/1674-4926/34/12/125007
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L Zhou, D Y Wu, F Jiang, Z Jin, X Y Liu. A 10 Gsps 8 bit digital-to-analog converter with a built-in self-test circuit[J]. J. Semicond., 2013, 34(12): 125007. doi: 10.1088/1674-4926/34/12/125007.
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A 10 Gsps 8 bit digital-to-analog converter with a built-in self-test circuit
DOI: 10.1088/1674-4926/34/12/125007
More Information
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Abstract
We present a 10 Gsps 8 bit digital-to-analog converter (DAC) with a novel built-in self-test (BIST) circuit, which makes it possible to evaluate the DAC's performance without a complicated test setup. Design considerations and test results are included. According to the test results, the DAC core and the BIST circuit are able to work under 10 GHz. The chip is fabricated in 0.18 μm SiGe HBTs with ft of 100 GHz. The DAC core occupies a die size of 260×250 μm2.-
Keywords:
- DAC,
- BIST,
- SiGe HBT,
- ultra-high-speed,
- optical communication
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References
[1] Qian D Y, Cvijetic N, Hu J Q, et al. 40-Gb/s MIMO-OFDM-PON using polarization multiplexing and direct-detection. Optical Fiber Communication Conference (OFC), San Diego, CA, 2009 http://ieeexplore.ieee.org/document/5032610/keywords[2] Haider S, Gustat H. A 30 GS/s 4-bit binary weighted DAC in SiGe BiCMOS technology. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Boston, MA, 2007:46 http://ieeexplore.ieee.org/document/4351836/authors[3] Nagatani M, Nosaka H, Yamanaka S, et al. A 32-GS/s 6-bit double-sampling DAC in InP HBT technology. IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Greensboro, NC, 2009:1 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5315628[4] Khafaji M, Gustat H, Scheytt C. A 6 bit linear binary RF DAC in 0.25μm SiGe BiCMOS for communication systems. IEEE Microwave Symposium Digest (MTT), Anaheim, CA, 2010:916[5] Khafaji M, Gustat H, Sedighi B, et al. A 6-bit fully binary digital-to-analog converter in 0.25-μm SiGe BiCMOS for optical communications. IEEE Trans Microw Theory Tech, 2011, 59:2254 doi: 10.1109/TMTT.2011.2161879[6] Alpert T, Lang F, Ferenci D, et al. A 28 GS/s 6 b pseudo segmented current steering DAC in 90nm CMOS. IEEE International Microwave Symposium (IMS), Baltimore, MD, 2011:1 http://ieeexplore.ieee.org/document/5973128/[7] Nagatani M, Nosaka H, Sano K, et al. A 60-GS/s 6-bit DAC in 0.5-μm InP HBT technology for optical communications systems. IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Waikoloa, HI, 2011:1[8] Nagatani M, Nosaka H, Yamanaka S, et al. Ultrahigh-speed low-power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems. IEEE J Solid-State Circuits, 2011, 46:2215 doi: 10.1109/JSSC.2011.2163211[9] Greshishchev Y M, Pollex D, Wang S C, et al. A 56 GS/s 6 b DAC in 65 nm CMOS with 256×6b memory. IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2011:194 http://ieeexplore.ieee.org/document/5746279/keywords[10] Lin C H, Bult K. A 10-b, 500M-Sample/s CMOS DAC in 0.6 mm2. IEEE J Solid-State Circuits, 1998, 43:1948[11] Schvan P, Pollex D, Bellingrath T. A 22GS/s 6b DAC with integrated digital ramp generator. IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2005:122[12] Halder S, Gustat H, Scheytt C, et al. A 20GS/s 8-bit current steering DAC in 0.25μm SiGe BiCMOS technology. IEEE European Microwave Integrated Circuit Conference (EuMIC), Amsterdam, 2008:147 -
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