Fig. 1.
At-speed transition test timing.
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| Citation: |
Wei Lin, Wenlong Shi. A new circuit for at-speed scan SoC testing[J]. Journal of Semiconductors, 2013, 34(12): 125012. doi: 10.1088/1674-4926/34/12/125012
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W Lin, W L Shi. A new circuit for at-speed scan SoC testing[J]. J. Semicond., 2013, 34(12): 125012. doi: 10.1088/1674-4926/34/12/125012.
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Abstract
It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design. -
References
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