Fig. 1.
PCM circuit structure.
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| Citation: |
Xiao Hong, Houpeng Chen, Zhitang Song, Daolin Cai, Xi Li. A low jitter PLL clock used for phase change memory[J]. Journal of Semiconductors, 2013, 34(2): 025012. doi: 10.1088/1674-4926/34/2/025012
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X Hong, H P Chen, Z T Song, D L Cai, X Li. A low jitter PLL clock used for phase change memory[J]. J. Semicond., 2013, 34(2): 025012. doi: 10.1088/1674-4926/34/2/025012.
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A low jitter PLL clock used for phase change memory
DOI: 10.1088/1674-4926/34/2/025012
More Information
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Abstract
A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.-
Keywords:
- PLL,
- PFD,
- charge pump,
- VCO,
- PCM
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References
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