Citation: |
Meile Wu, Xiaoshi Jin, Rongyan Chuai, Xi Liu, Jong-Ho Lee. Simulation study on short channel double-gate junctionless field-effect transistors[J]. Journal of Semiconductors, 2013, 34(3): 034004. doi: 10.1088/1674-4926/34/3/034004
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M L Wu, X S Jin, R Y Chuai, X Liu, J H Lee. Simulation study on short channel double-gate junctionless field-effect transistors[J]. J. Semicond., 2013, 34(3): 034004. doi: 10.1088/1674-4926/34/3/034004.
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Simulation study on short channel double-gate junctionless field-effect transistors
DOI: 10.1088/1674-4926/34/3/034004
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Abstract
We study the characteristics of short channel double-gate (DG) junctionless (JL) FETs by device simulation. Output Ⅰ-Ⅴ characteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed. Distributions of electron concentration, electric field and potential in the body channel region are also analyzed. Comparisons with conventional inversion-mode (IM) FETs, which can demonstrate the advantages of JL FETs, have also been performed. -
References
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