1. Introduction

Voltage controlled oscillators (VCOs) are key building blocks in millimeter-wave (mm-wave) integrated circuits due to the increasing demand for wide band and high data rate communication systems. Therefore, great efforts have been made to enhance the performance of mm-wave VCOs^[1-3]. For VCOs employing an LC tank as a resonator, such as the Colpitts or cross-coupled VCO, the oscillation frequency is determined by the values of the tank inductors and capacitors. Hence, it is important to study the parasitic effects which affect the total equivalent values of the tank. Recently, as implemented in high frequencies, LC tank VCOs face increased challenges of coupling effects due to miniaturization. Tank inductors need to be placed very close to each other in layout. Although special technologies have been applied to de-couple those inductors on a process level, such as guard-rings and deep n-well technology, there are still strong coupling effects between the adjacent inductors introducing parameter drift. Previous works on coupling inductors^{[4, 5]} were not intended for application in VCO design. Another key issue in VCOs is to improve power efficiency while exhibiting high output power. To achieve high efficiency, the CMOS VCO is significant in lowering the whole power dissipation in mm-wave systems. Recently, CMOS VCOs operating at around 50 GHz or higher regularly have low output power and low efficiency^{[6, 7]}.

In this work, an extraction of the coupling effects in a VCO's tank inductor has been adopted to obtain the accuracy value of the inductor. A high quality factor ($Q$-factor) metal-oxide-metal (MOM) capacitor has been implemented to gain high power efficiency. Section 2 extracts the coupling effects. The proposed VCO topology and measured results are illustrated in Sections 3 and 4. Conclusions are drawn in Section 5.

2. Coupling effects of inductors

Different from Ref.[4], adjacent cascaded inductors are focused upon in this work, corresponding to the implementation in a VCO's LC tank. Figures 1(a) and 1(b) illustrate the micro-photograph of the element and cascaded fabricated spiral inductor. Except for the number of cascaded inductor, the sizes of the inductors are identical in this work. The inner diameter of each inductor is 11 $\mu$m, the width of inductor is 3 $\mu$m, and the gap between metal lines is 3 $\mu$m, respectively. The edge distance between two adjacent inductors is set to 40 $\mu$m^[4].

The effective inductance ($L_{\rm eff})$ and the effective $Q$-factor ($Q_{\rm eff})$ are extracted from the measured $S$-parameters where de-embedding technology has been implemented^[5]. As shown in Fig. 2(a), two de-embedded $S$-parameters of the elemental inductor are connected in series to represent the cascaded inductor without coupling effects. The cascaded inductor considering coupling characteristic is depicted in Fig. 2(b). Both are single-ended driven and the characteristics are compared with simulated results based on HFSS. The simulated and measured $L_{\rm eff}$ and $Q_{\rm eff}$ with or without coupling effects are shown in Fig. 3.

3. The proposed VCO topology

The proposed VCO is indicated in Fig. 4, in which the cross coupled pair is utilized to compensate the loss in resonators, such as parasitic resistance. The core consists of a negative channel metal oxide semiconductor (NMOS) cross coupled pair (M1 and M2), which provides negative resistance, and an LC tank ($C_{1}$, $C_{\rm v1}$, $C_{2}$, $C_{\rm v2}$, $L_{1}$, $L_{2})$. A positive channel metal oxide semiconductor (PMOS) tail transistor M3 is employed as the current source to reduce the $1/f$ noise^[7].

3.1 LC tank

The schematic of the tank inductor's structure is shown in Fig. 5(a) and the simulation results are indicated in Fig. 5(b), with and without coupling effects. Based on the results observed in Section 2, the edge distance is set to 40 $\mu$m, trading off between the inductor sizes and coupling effects. Simulated results show an 8.6% reduction in $L_{\rm eff}$ which means an actual 115 pH for half the tank regarding the mutual inductance.

The half equivalent circuit of the proposed core VCO is featured in Fig. 6, where the coupled pair M1 and M2 is modeled as a negative conductance $-G_{\rm m1}$ and a shunt capacitance $C_{\rm pm1}$ representing parasitic capacitance caused by transistors. The lossy element is represented as $G_{\rm p}$, whereas $C_{\rm pBUF}$ is buffer input capacitance. There is a trade-off between output power and frequency tuning range (FTR). To meet the start-up condition, the channel width of M1/M2 only needs to be set as 8 $\mu$m. Under the identical conditions such as the same \textit{LC} tank and the same direct current (DC) supply, the enlargement of the channel width could increase the input current of the core VCO, which can indeed be exploited to achieve a higher output power and thus increase efficiency.^[8] Hence, to gain a high output swing and efficiency the designed channel width needs to be extended to 12 $\mu$m. However, simultaneously, the increased parasite capacitance of the larger transistor will add to the LC tank in parallel. While the other passive LC tank stays the same, the added bypass parasite capacitance reduces the FTR. Another trade-off exists between phase noise and FTR. To improve the phase noise performance, the $Q$-factor of the LC tank needs to be enhanced^[9]. As in Ref.[7], the $Q$-factor of the tank is more limited by the varactor but not the inductor in mm-wave regime. To compensate the low $Q$-factor caused by the accumulation MOS (AMOS) varactor, a high $Q$-factor MOM capacitor has been connected in parallel with the AMOS varactor to form the varactor $C_{\rm v1}$ and $C_{\rm v2}$, as shown in Fig. 7. The varactor $C_{\rm v1}$ and $C_{\rm v2}$ are connected with MOM capacitor $C_{1}$ and $C_{2}$, respectively. As depicted in Fig. 7, such a configuration of capacitors in the tank could enhance the $Q$-factor compared with the only adoption of low $Q$-factor AMOS varactors. However, by adding fixed MOM capacitors, such a configuration could reduce the FTR of the VCO at the same time.

3.2 Buffer

In this work, a two-stage buffer amplifier with transistors in common-source (CS) configuration is employed^[2] to further boost the output power, in which the first stage transistor size is tapered to minimize the effect of the buffers on the LC tank. The circuit schematic of the output buffer is shown in Fig. 8. The buffer's supply is cut down to 0.7 V to achieve high efficiency whereas keeping good linearity of the output swing.

In order to further maximize the output swing and the efficiency of the VCO, the bias of the second stage transistor has been adjusted to hold the transistor working in the class-AB region. As shown in Fig. 8, the gate bias of M6 is set as 0.7 V, while M7 is biased at 0.55 V. The first stage transistor is chosen to be small for good isolation between the second stage transistor and the core VCO, while keeping the signal's linearity. The second stage transistor is chosen to be large for high power output, while it operates in class-AB to cut off the power consumption thus to enhance power efficiency. Because the core VCO output and the tank share the same terminals, the attached buffer amplifier has an influence on the tank impedance. Hence, the buffer needs to be carefully designed with the impedance matching. In this work, the on-chip inductors, with the inductance of 165 pH and 220 pH respectively, have been implemented for their ease of matching and low insertion loss. With respect to the operation in mm-wave, such implementations could enhance the VCO's efficiency.

4. Measurement results

By utilizing a 65 nm CMOS 1P8M standard process from UMC, a 50 GHz cross-coupled VCO with differential outputs is implemented in the core circuit. Buffers are used to isolate the core circuit from subsequent circuits and to achieve high output power with high efficiency. Figure 9 shows the micrograph of the fabricated circuit, in which a symmetrical architecture and layout are implemented to ensure the fully differential operation of M1 and M2. The total chip area, including the DC and radio frequency (RF) pads, is 0.6 $\times$ 0.45 mm$^{2}$, where the active area only occupies 0.45 $\times$ 0.3 mm$^{2}$. The VCO is characterized on-wafer, using an Agilent N9030A PXA for frequency, power and phase noise measurements. The spectrum analyzer is connected to one of the VCO's outputs, while the other one is terminated by a 50 $\Omega$ load. Corrections for cable loss and single-ended measurement are applied.^[8] At the maximum linearity bias point the VCO core draws 12 mA from 1 V supply and the buffers draw 11 mA from 0.7 V supply, with the total 19.7 mW power consumption.

As illustrated in Fig. 10(a), the measured oscillation frequency is from 48.98 to 50.88 GHz, which corresponds to a FTR of 3.8%, with the controlled voltage, $V_{\rm TUNE}$, from 0 to 1.8 V. The simulation results with considering the adjacent inductors' coupling effect show better matching with measurements than the results derived from the simulation without considering the adjacent inductors' coupling effect. The nearly 10% differences in the simulated oscillation frequencies without regarding the coupling effect are because of the inaccurate effective inductance of the tank inductor. The figure illustrates that to get an accurate oscillation frequency, the coupling effect of the adjacent inductor should be considered in the LC tank VCO's design. As featured in Fig. 10(b), the output power simulation results with and without considering the adjacent inductors' coupling are almost the same. It is because the parasitic resistor depends on the lossy substrate, the metal conductance and size, but has little relationship with the coupling effect. Figure 10(b) shows that the one-side output power is around $-0.5$ dBm over the whole tuning voltage interval in which the maximum one-side output power of 0.5 dBm is achieved at 49.71 GHz, whereas the simulated one-side output power is around 0.5 dBm. The combined output power is more than 2.5 dBm over the whole operation frequencies, while achieving a maximum 3.5 dBm output power. This VCO also achieves a maximum efficiency of 11.4% and an average efficiency of 9.1% over the entire FTR, respectively. In this paper, larger transistors in the tank are adopted for the potentially high headroom of voltage swing and thus linearity, high $Q$-factor on-chip inductors have been implemented for low loss matching and buffers working in Class-AB region have been employed. The high output power and efficiency performance could be ascribed to such changes. As far the currently available literature by the authors is concerned, this is the highest output power when adopting the CMOS process around V-band or higher.

Measured phase noise at 50.88 GHz is depicted in Fig. 11, where the minimum value of $-87$ dBc/Hz and $-100$ dBc/Hz are achieved at 1 MHz and 10 MHz offset, respectively. Table 1 shows the performance in comparison with some other published VCOs. A modified FoM including output power^[8] demonstrates that the presented VCO exhibits good performance.

5. Conclusion

In this paper, the coupling effects between cascaded inductors have been studied and then implemented in an LC cross-coupled CMOS VCO design. The VCO exhibits an average 2.5 dBm output power and average 9.1% efficiency over the whole FTR while only consumes 19.7 mW, whereas achieves a minimum phase noise of -87 dBc/Hz at 1 MHz offset and a FTR of 3.8% (48.98 to 50.88 GHz). The maximum output power of 3.5 dBm and maximum efficiency of 11.4% are achieved for the VCO.