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J. Semicond. > 2013, Volume 34 > Issue 8 > 084001

SEMICONDUCTOR DEVICES

ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs

T. Bentrcia1, F. Djeffal2, 3, and E. Chebaaki2

+ Author Affiliations

 Corresponding author: F. Djeffal, Email:faycal.djeffal@univ-batna.dz, faycaldzdz@hotmail.com

DOI: 10.1088/1674-4926/34/8/084001

PDF

Abstract: A fuzzy framework based on an adaptive network fuzzy inference system (ANFIS) is proposed to evaluate the relative degradation of the basic subthreshold parameters due to hot-carrier effects for nanoscale thin-film double-gate (DG) MOSFETs. The effect of the channel length and thickness on the resulting degradation is addressed, and 2-D numerical simulations are used for the elaboration of the training database. Several membership function shapes are developed, and the best one in terms of accuracy is selected. The predicted results agree well with the 2-D numerical simulations and can be efficiently used to investigate the impact of the interface fixed charges and quantum confinement on nanoscale DG MOSFET subthreshold behavior. Therefore, the proposed ANFIS-based approach offers a simple and accurate technique to study nanoscale devices, including the hot-carrier and quantum effects.

Key words: hot-carrier degradationANFISfuzzy computationsubthresholdquantum effectsthin film

In recent years, vibration energy harvesters have drawn more attention in the world. It can be used in many fields ranging from implanted devices and wearable electronic devices to mobile electronics and self-powered wireless network nodes[1-3]. There are three ways to convert vibration energy into electrical energy, namely electromagnetic, piezoelectric and electrostatic[4, 5]. Among these three harvesters, the electromagnetic harvester cannot produce a larger current but relative low voltage, so the design of management power circuit is more difficult. Because of the need for an external voltage source, the electrostatic harvester is impossible to be used in practical applications. Therefore most of the researchers have been working on the piezoelectric harvester, which has a high output voltage and a high efficiency of electromechanical energy conversion of piezoelectric.

As the key part of the piezoelectric vibration harvester, the piezoelectric materials mainly include lead zirconate titanate (PZT) piezoceramic, polyvinylidene fluoride (PVDF) polymer, polycrystalline zinc oxide (ZnO), aluminum nitride (AlN) and so on. AlN has proven to be the superior piezoelectric ceramic when it comes to energy harvester devices owing to its high energy density, moderate voltage levels, low dielectric constant and especially its compatibility with CMOS processes[6, 7]; furthermore it can be deposited easily at low temperatures and has already been widely used in the MEMS, microelectronic and microsensor industries[4].

A number of works have been devoted to fabricating the single beam harvester based on the AlN film[4-6, 8-15], but the harvester array based on the AlN film was rarely reported, the max output was about 1 μW. This paper presents the fabrication process and the measurement results of the harvester array based on the AlN film. The characterizations, such as load characteristics and frequency characteristics, have been done in the final part.

Table  1.  The comparison of energy harvester based on AlN film
DownLoad: CSV  | Show Table

Based on the piezoelectric effect, the vibration energy harvester array converts the environmental vibration energy in the surrounding to electric energy. The vibration energy harvester array consists of five cantilevers ended with one attached mass. The three advantages of the design are that the grooves between cantilevers allow the air to flow smoothly and reduce the air damping ratio, the cantilever arrays connected in series make the currents increase greatly, one attached mass should guarantee the consistency of the five cantilevers resonant frequency. Equation (1) in Ref. [16] shows that the air damping ratio decreases with decreasing the width of cantilever when keeping other parameters constant. The currents increasing can be explained by Kirchhoff's current law in Ref. [17]. The one attached mass ensures that the 5 cantilevers can vibrate in phase and the piezoelectric elements can be connected directly in parallel or series. The structure in this paper is different from the single cantilever structure reported in reference[4, 5, 10-13, 18, 19], but alike to the structure in Ref. [3]. The schematic structure is shown in Fig. 1. The fabricating process of the vibration piezoelectric energy harvester arrays is shown in Fig. 2.

Figure  1.  The structure of vibration energy harvester array
Figure  2.  The process of fabricating a vibration piezoelectric energy harvester

ξsq=νb22ρag30hω,

(1)

where ν, b, ρa, g, h and ω are the air viscosity, the cantilever width, the air density, the distance of cantilever to the fixture, the thickness of the cantilever and the response frequency, respectively.

N-type 100 mm diameter, double-sided-polished, (100) CZ silicon (Si) of resistivity 2-4 Ωcm silicon on insulator (SOI) wafers are prepared for fabricating vibration energy harvester arrays. The thickness of the device layer that is the top layer of the SOI wafer is about 50 ± 1 μm, and the bottom silicon layer of the SOI wafer is about 450 ± 2 μm. The thermal buried oxide is a thickness 1.0 ± 0.05 μm between the device layer and bottom silicon layer. After the wafers were cleaned in RCA1 and RCA2 solutions, a 300 nm thickness silicon oxygen layer as a dielectric layer was grown on both sides of the SOI wafers. Then patterned stacks of 25 nm AlN (seed layers), 200 nm Mo (bottom electrode) and 1.0 μm AlN (crystalline piezoelectric material) were deposited by the magnetron system. Following that, Al as the top electrode material was deposited and patterned and the deep reactive ions etch (DRIE) system was used to produce grooves. In the end, the SiO2 layer between the SOI wafer was removed by the reactive ions etch (RIE) after the cantilever structure was released by DRIE. Finally, the wafer was diced and wire bond, then individual devices can be electrically tested. Figure 3 shows the picture of the fabricated vibration piezoelectric energy harvester arrays.

Figure  3.  The picture of vibration energy harvester array

The power out of piezoelectric vibration piezoelectric energy harvester arrays is mainly dependent on the properties of AlN and the structure of the harvester array. So the X-ray diffraction (XRD) is utilized to characterize the AlN film, as shown in Fig. 4. The X-ray rocking curve measurement indicates the film has the crystal orientation (002) and the intensity reaches 1.1 × 105 counts, the full width height maximum (FWHM) is 1.9. The FWHM of the diffraction peak in the XRD pattern refers to the general quality of the AlN film. The smaller the FWHM is, the higher the piezoelectric quality is.

Figure  4.  The rocking curve of AlN films

The vibration piezoelectric energy harvester can be equivalent to the two-port network as shown in Fig. 5. While Vs is set as an exited source, Vo is the voltage value dissipated on the equivalent load, while Zs and Zl is equivalent to the impedance of the harvester array and the load respectively. The power out is formatted as follows:

Figure  5.  Dual-port network equivalent diagrams

P0=V20Zl,thatisp0=V2sZl(Zs+Zl)2.

(2)

From Eq. (1), an conclusion can be drawn that the max power dissipated on the load can be attained when and only when Zs and Zl are equal.

The power out and open circuit voltage of the harvester arrays were detected when a series of different load impedances were applied, as shown in Fig. 6. The varying of the resonant frequency and the output voltage with the applied acceleration were obtained as shown in Fig. 7. The equivalent impedance of 80 kΩ and the maximum power output of 30.4 μW can be firstly obtained based on Fig. 6. As far as we know, the power output of the proposed device is really high compared to the harvester arrays based on AlN thin films. It can be seen in Fig. 7 that the resonant frequency varied little with acceleration increasing, but open voltage increased lineally with acceleration increasing. The bandwidth is a little narrow, so the future work will focus on the bandwidth broadening. The main reason for the power output in this paper, more than that of the harvester in Ref. [3] is that the value of 0.9g is applied in our experience, while the power output is proportional to g2. The relations between power out and accelerations will be presented in other papers.

Figure  6.  The open circuit voltage and power out versus resistance under 0.9g
Figure  7.  The open circuit voltage and frequency versus acceleration with loads of 80 kΩ

In this work the fabrication of piezoelectric vibration energy harvester arrays based on AlN thin film deposited by pulsed-DC magnetron sputtering is presented. The maximum power output is about 30.4 μW at an acceleration of 0.9g for the 80 kΩ resistance when the resonant frequency is 204 Hz, its power density reaches about 1.4 mW/cm3. The findings will be applied widely in wireless sensor networks (WSN) and other fields such as portable electronic products. In the next step we will further focus our attention on the improvements of AlN properties and increase the high efficiency of electromechanical energy conversion to increase the power density and decrease the resonance frequency.



[1]
Kaur H, Kabra S, Haldar S, et al. An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET. Microelectron J, 2007, 38:352 doi: 10.1016/j.mejo.2007.01.003
[2]
Amat E, Rodrìguez R, Nafrìa M, et al. Channel hot-carrier degradation under AC stress in short channel nMOS devices with high-k gate stacks. Microelectron Eng, 2009, 86:1908 doi: 10.1016/j.mee.2009.03.031
[3]
Ghosh P, Haldar S, Gupta R S, et al. An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET. Microelectron J, 2012, 43:17 doi: 10.1016/j.mejo.2011.10.001
[4]
International Technology Roadmap for Semiconductors (ITRS), Published online at http://public.itrs.net, 2009
[5]
Difrenza R, Linares P, Ghibaudo G. The impact of short channel and quantum effects on the MOS transistor mismatch. Solid-State Electron, 2003, 47:1161 doi: 10.1016/S0038-1101(03)00033-9
[6]
Bentrcia T, Djeffal F. Compact modeling of multi-gate MOSFET including hot-carrier effects. CMOS Technology:Electrical Engineering Developments Series, Vol. 1. Chap. 4. New York:Nova Publishers, 2011
[7]
Pagey M P. Hot-carrier reliability simulation in aggressively scaled MOS transistors. PhD Dissertation, Electrical Engineering Department, Vanderbilt University, Nashville, Tennessee, USA, 2003 http://etd.library.vanderbilt.edu/available/etd-12032003-100902/unrestricted/Thesis.pdf
[8]
Prégaldiny F, Lallement C, Mathiot D. Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface-potential-based MOSFET model. Solid-State Electron, 2004, 48:781 doi: 10.1016/j.sse.2003.12.010
[9]
Ghoggali Z, Djeffal F, Lakhdar N. Analytical analysis of nanoscale double-gate MOSFETs including the hot-carrier degradation effects. Int J Electron, 2010, 97:119 doi: 10.1080/00207210902894746
[10]
Bendib T, Djeffal F. Electrical performance optimization of nanoscale double-gate MOSFETs using multi-objective genetic algorithms. IEEE Trans Electron Devices, 2011, 58:3743 doi: 10.1109/TED.2011.2163820
[11]
Bentrcia T, Djeffal F, Benhaya A. Continuous analytic Ⅳ model for GS DG MOSFETs including hot-carrier degradation effects. Journal of Semiconductors, 2012, 33:014001 doi: 10.1088/1674-4926/33/1/014001
[12]
Djeffal F, Bentrcia T, Abdi M A, et al. Drain current model for undoped gate stack double gate (GSDG) MOSFETs including the hot-carrier degradation effects. Microelectron Reliab, 2011, 51:550 doi: 10.1016/j.microrel.2010.10.002
[13]
Djeffal F, Bentrcia T, Bendib T. An analytical drain current model for undoped GSDG MOSFETs including interfacial hot-carrier effects. Phys Status Solidi C, 2011, 8:907 doi: 10.1002/pssc.201000158
[14]
Tyaginov S E, Starkov I A, Triebl O, et al. Interface traps density-of-states as a vital component for hot-carrier degradation modeling. Microelectron Reliab, 2010, 50:1267 doi: 10.1016/j.microrel.2010.07.030
[15]
Eisberg R, Renick R. Notes on modern physics. John Wiley and Sons, NY, 1969
[16]
Djeffal F, Bendib T, Abdi M A. A two-dimensional semi-analytical analysis of the subthreshold-swing behavior including free carriers and interfacial traps effects for nanoscale double-gate MOSFETs. Microelectron J, 2011, 42:1391 doi: 10.1016/j.mejo.2011.09.008
[17]
Ho C S, Huang K Y, Tang M, et al. An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect. Microelectron Reliab, 2005, 45:1144 doi: 10.1016/j.microrel.2004.10.007
[18]
Mahapatra S, Parikh C D, Rao V R, et al. A Comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFET's using a novel charge pumping technique. IEEE Trans Electron Devices, 2000, 47:171 doi: 10.1109/16.817583
[19]
Singh A K. An analytical study of hot-carrier degradation effects in sub-micron MOS devices. The European Physical Journal Applied Physics, 2008, 42(2):87 doi: 10.1051/epjap:2008047
[20]
Naseh S, Deen M J, Chen C. Hot-carrier reliability of submicron nMOSFETs and integrated nMOS low noise amplifiers. Microelectron Reliab, 2006, 46:201 doi: 10.1016/j.microrel.2005.04.009
[21]
Zadeh L A. Outline of a new approach to the analysis of complex systems and decision processes. IEEE Trans Syst, Man, Cybernetics, 1973, 3:28 http://www.oalib.com/references/13118707
[22]
Jang J. ANFIS:adaptive-network-based fuzzy inference system. IEEE Trans Syst Man Cybernytics, 1993, 23:665 doi: 10.1109/21.256541
[23]
Lo S P. An adaptive-network based fuzzy inference system for prediction of work piece surface roughness in end milling. Journal of Materials Processing Technology, 2003, 142: 665
[24]
Ying L C, Pan M C. Using adaptive network based fuzzy inference system to forecast regional electricity loads. Energy Conversion and Management, 2008, 49:205 doi: 10.1016/j.enconman.2007.06.015
[25]
Akdemïr B, Günes S, Oran B, et al. Prediction of cardiac end-systolic and end-diastolic diameters in m-mode values using adaptive neural fuzzy inference system. Expert Systems with Applications, 2010, 37:5720 doi: 10.1016/j.eswa.2010.02.038
[26]
Singh M. Adaptive network-based fuzzy inference systems for sensorless control of PMSG based wind turbine with power quality improvement features. PhD Dissertation, University of Quebec, MONTREAL, 16 JULY 2010
[27]
Lawson C L, Hanson R J. Solving least squares problems. Englewood Cliffs, NJ: Prentice-Hall, 1974
[28]
Nariman-Zadeh N, Darvizeh A, Dadfarmai M H. Design of ANFIS networks using hybrid genetic and SVD methods for the modelling of explosive cutting process. Journal of Materials Processing Technology, 2004, 155:1415 doi: 10.1007/s12239-009-0020-6
[29]
Jiang H M, Kwong C K, Ip W H, et al. Modeling customer satisfaction for new product development using a PSO-based ANFIS approach. Applied Soft Computing, 2012, 12:726 doi: 10.1016/j.asoc.2011.10.020
[30]
Atlas User's Manual: Device Simulation Software, 2008
[31]
Djeffal F, Ghoggali Z, Dibi Z, et al. Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges. Microelectron Reliab, 2009, 49:377 doi: 10.1016/j.microrel.2008.12.011
[32]
Bentrcia T, Djeffal F, Abdi M A, et al. An accurate two dimensional threshold voltage model for nanoscale GCGS DGMOSFET including traps effects. 3rd IEEE International Conference on Signals, Circuits and Systems, Djerba, Tunisia, 2009 doi: 10.1007/978-94-017-8832-8_25
[33]
Bentrcia T, Djeffal F, Arar D. An analytical two dimensional subthreshold current model for nanoscale GCGS DG MOSFET including interfacial traps effects. Rev Sci Technol, 2010, 1:103 doi: 10.1007%2Fs10825-010-0329-4.pdf
[34]
Djeffal F, Meguellati M, Benhaya A. A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs. Physica E:Low-Dimensional Systems and Nanostructures, 2009, 41:1872 doi: 10.1016/j.physe.2009.08.002
Fig. 1.  Illustrative representation of ANFIS with two input parameters and two MFs.

Fig. 2.  3-D cross-sectional view of the symmetrical DG MOSGET including interface traps.

Fig. 3.  Variation in threshold voltage DGMOSFET with and without traps as a function of channel length (tsi = 2 nm).

Fig. 4.  Variation in threshold voltage DGMOSFET with and without traps as a function of channel width (L= 75 nm).

Fig. 5.  Variation in DIBL DGMOSFET with and without traps as a function of channel length (tsi = 3 nm).

Fig. 6.  Variation in subthreshold current DGMOSFET with and without traps as a function of channel length (tsi = 4 nm).

Fig. 7.  Gaussian combination membership functions of the channel length input parameter in the case of threshold voltage degradation.

Fig. 8.  Gaussian combination membership functions of the channel thickness input parameter in the case of threshold voltage degradation.

Fig. 9.  ANFIS controller rule surface for the threshold voltage relative degradation.

Fig. 10.  ANFIS controller rule surface for the DIBL relative degradation

Fig. 11.  ANFIS controller rule surface for the subthreshold current relative degradation.

Fig. 12.  Regression curve of the threshold voltage relative degradation for the training data.

Fig. 13.  Regression curve of the threshold voltage relative degradation for the testing data.

Fig. 14.  Regression curve of the DIBL relative degradation for the testing data.

Fig. 15.  Regression curve of the subthreshold current relative degradation for the testing data.

Table 1.   Device design and simulation parameters.

Table 2.   Summary of the main obtained results.

[1]
Kaur H, Kabra S, Haldar S, et al. An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET. Microelectron J, 2007, 38:352 doi: 10.1016/j.mejo.2007.01.003
[2]
Amat E, Rodrìguez R, Nafrìa M, et al. Channel hot-carrier degradation under AC stress in short channel nMOS devices with high-k gate stacks. Microelectron Eng, 2009, 86:1908 doi: 10.1016/j.mee.2009.03.031
[3]
Ghosh P, Haldar S, Gupta R S, et al. An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET. Microelectron J, 2012, 43:17 doi: 10.1016/j.mejo.2011.10.001
[4]
International Technology Roadmap for Semiconductors (ITRS), Published online at http://public.itrs.net, 2009
[5]
Difrenza R, Linares P, Ghibaudo G. The impact of short channel and quantum effects on the MOS transistor mismatch. Solid-State Electron, 2003, 47:1161 doi: 10.1016/S0038-1101(03)00033-9
[6]
Bentrcia T, Djeffal F. Compact modeling of multi-gate MOSFET including hot-carrier effects. CMOS Technology:Electrical Engineering Developments Series, Vol. 1. Chap. 4. New York:Nova Publishers, 2011
[7]
Pagey M P. Hot-carrier reliability simulation in aggressively scaled MOS transistors. PhD Dissertation, Electrical Engineering Department, Vanderbilt University, Nashville, Tennessee, USA, 2003 http://etd.library.vanderbilt.edu/available/etd-12032003-100902/unrestricted/Thesis.pdf
[8]
Prégaldiny F, Lallement C, Mathiot D. Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface-potential-based MOSFET model. Solid-State Electron, 2004, 48:781 doi: 10.1016/j.sse.2003.12.010
[9]
Ghoggali Z, Djeffal F, Lakhdar N. Analytical analysis of nanoscale double-gate MOSFETs including the hot-carrier degradation effects. Int J Electron, 2010, 97:119 doi: 10.1080/00207210902894746
[10]
Bendib T, Djeffal F. Electrical performance optimization of nanoscale double-gate MOSFETs using multi-objective genetic algorithms. IEEE Trans Electron Devices, 2011, 58:3743 doi: 10.1109/TED.2011.2163820
[11]
Bentrcia T, Djeffal F, Benhaya A. Continuous analytic Ⅳ model for GS DG MOSFETs including hot-carrier degradation effects. Journal of Semiconductors, 2012, 33:014001 doi: 10.1088/1674-4926/33/1/014001
[12]
Djeffal F, Bentrcia T, Abdi M A, et al. Drain current model for undoped gate stack double gate (GSDG) MOSFETs including the hot-carrier degradation effects. Microelectron Reliab, 2011, 51:550 doi: 10.1016/j.microrel.2010.10.002
[13]
Djeffal F, Bentrcia T, Bendib T. An analytical drain current model for undoped GSDG MOSFETs including interfacial hot-carrier effects. Phys Status Solidi C, 2011, 8:907 doi: 10.1002/pssc.201000158
[14]
Tyaginov S E, Starkov I A, Triebl O, et al. Interface traps density-of-states as a vital component for hot-carrier degradation modeling. Microelectron Reliab, 2010, 50:1267 doi: 10.1016/j.microrel.2010.07.030
[15]
Eisberg R, Renick R. Notes on modern physics. John Wiley and Sons, NY, 1969
[16]
Djeffal F, Bendib T, Abdi M A. A two-dimensional semi-analytical analysis of the subthreshold-swing behavior including free carriers and interfacial traps effects for nanoscale double-gate MOSFETs. Microelectron J, 2011, 42:1391 doi: 10.1016/j.mejo.2011.09.008
[17]
Ho C S, Huang K Y, Tang M, et al. An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect. Microelectron Reliab, 2005, 45:1144 doi: 10.1016/j.microrel.2004.10.007
[18]
Mahapatra S, Parikh C D, Rao V R, et al. A Comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFET's using a novel charge pumping technique. IEEE Trans Electron Devices, 2000, 47:171 doi: 10.1109/16.817583
[19]
Singh A K. An analytical study of hot-carrier degradation effects in sub-micron MOS devices. The European Physical Journal Applied Physics, 2008, 42(2):87 doi: 10.1051/epjap:2008047
[20]
Naseh S, Deen M J, Chen C. Hot-carrier reliability of submicron nMOSFETs and integrated nMOS low noise amplifiers. Microelectron Reliab, 2006, 46:201 doi: 10.1016/j.microrel.2005.04.009
[21]
Zadeh L A. Outline of a new approach to the analysis of complex systems and decision processes. IEEE Trans Syst, Man, Cybernetics, 1973, 3:28 http://www.oalib.com/references/13118707
[22]
Jang J. ANFIS:adaptive-network-based fuzzy inference system. IEEE Trans Syst Man Cybernytics, 1993, 23:665 doi: 10.1109/21.256541
[23]
Lo S P. An adaptive-network based fuzzy inference system for prediction of work piece surface roughness in end milling. Journal of Materials Processing Technology, 2003, 142: 665
[24]
Ying L C, Pan M C. Using adaptive network based fuzzy inference system to forecast regional electricity loads. Energy Conversion and Management, 2008, 49:205 doi: 10.1016/j.enconman.2007.06.015
[25]
Akdemïr B, Günes S, Oran B, et al. Prediction of cardiac end-systolic and end-diastolic diameters in m-mode values using adaptive neural fuzzy inference system. Expert Systems with Applications, 2010, 37:5720 doi: 10.1016/j.eswa.2010.02.038
[26]
Singh M. Adaptive network-based fuzzy inference systems for sensorless control of PMSG based wind turbine with power quality improvement features. PhD Dissertation, University of Quebec, MONTREAL, 16 JULY 2010
[27]
Lawson C L, Hanson R J. Solving least squares problems. Englewood Cliffs, NJ: Prentice-Hall, 1974
[28]
Nariman-Zadeh N, Darvizeh A, Dadfarmai M H. Design of ANFIS networks using hybrid genetic and SVD methods for the modelling of explosive cutting process. Journal of Materials Processing Technology, 2004, 155:1415 doi: 10.1007/s12239-009-0020-6
[29]
Jiang H M, Kwong C K, Ip W H, et al. Modeling customer satisfaction for new product development using a PSO-based ANFIS approach. Applied Soft Computing, 2012, 12:726 doi: 10.1016/j.asoc.2011.10.020
[30]
Atlas User's Manual: Device Simulation Software, 2008
[31]
Djeffal F, Ghoggali Z, Dibi Z, et al. Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges. Microelectron Reliab, 2009, 49:377 doi: 10.1016/j.microrel.2008.12.011
[32]
Bentrcia T, Djeffal F, Abdi M A, et al. An accurate two dimensional threshold voltage model for nanoscale GCGS DGMOSFET including traps effects. 3rd IEEE International Conference on Signals, Circuits and Systems, Djerba, Tunisia, 2009 doi: 10.1007/978-94-017-8832-8_25
[33]
Bentrcia T, Djeffal F, Arar D. An analytical two dimensional subthreshold current model for nanoscale GCGS DG MOSFET including interfacial traps effects. Rev Sci Technol, 2010, 1:103 doi: 10.1007%2Fs10825-010-0329-4.pdf
[34]
Djeffal F, Meguellati M, Benhaya A. A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs. Physica E:Low-Dimensional Systems and Nanostructures, 2009, 41:1872 doi: 10.1016/j.physe.2009.08.002
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    Zhengguo Shang, Dongling Li, Zhiyu Wen, Xingqiang Zhao. The fabrication of vibration energy harvester arrays based on AlN piezoelectric film[J]. Journal of Semiconductors, 2013, 34(11): 114013. doi: 10.1088/1674-4926/34/11/114013
    Z G Shang, D L Li, Z Y Wen, X Q Zhao. The fabrication of vibration energy harvester arrays based on AlN piezoelectric film[J]. J. Semicond., 2013, 34(11): 114013. doi: 10.1088/1674-4926/34/11/114013.
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    Received: 11 January 2013 Revised: 10 February 2013 Online: Published: 01 August 2013

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      Zhengguo Shang, Dongling Li, Zhiyu Wen, Xingqiang Zhao. The fabrication of vibration energy harvester arrays based on AlN piezoelectric film[J]. Journal of Semiconductors, 2013, 34(11): 114013. doi: 10.1088/1674-4926/34/11/114013 ****Z G Shang, D L Li, Z Y Wen, X Q Zhao. The fabrication of vibration energy harvester arrays based on AlN piezoelectric film[J]. J. Semicond., 2013, 34(11): 114013. doi: 10.1088/1674-4926/34/11/114013.
      Citation:
      T. Bentrcia, F. Djeffal, E. Chebaaki. ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs[J]. Journal of Semiconductors, 2013, 34(8): 084001. doi: 10.1088/1674-4926/34/8/084001 ****
      T. Bentrcia, F. Djeffal, E. Chebaaki. ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs[J]. J. Semicond., 2013, 34(8): 084001. doi: 10.1088/1674-4926/34/8/084001.

      ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs

      DOI: 10.1088/1674-4926/34/8/084001
      More Information
      • Corresponding author: F. Djeffal, Email:faycal.djeffal@univ-batna.dz, faycaldzdz@hotmail.com
      • Received Date: 2013-01-11
      • Revised Date: 2013-02-10
      • Published Date: 2013-08-01

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