1. Introduction

As the microchip manufacture process scales down, the low power and high dynamic range are becoming a bottle neck of the analog to digital converter (ADC), especially considering applications for the radio-frequency (RF) transceiver front-end of the wireless sensor network (WSN). Considering the modulation mode of quadrature phase shift keying (QPSK) for the wireless sensor network, a 20 MHz sample rate meets its bandwidth range, and a 6-bit design satisfies its resolution request and relaxes the limits of the radio-frequency (RF) transceiver front-end.

Since the successive approximation algorithm (SA algorithm) operation only requires one comparator, the successive approximation register analog to digital converter (SAR ADC) accomplishes higher efficiency contrasted with other types of ADCs. The conventional SAR ADC normally consists of a digital to analog converter (DAC), comparator, and control logic^[1-6]. Measurement results demonstrate that the comparator is the dominant cause of energy consumption. The traditional voltage comparator contains multiple stages of inefficient preamplifiers and latches. During the comparator operation, the preamplifier consumes the static power at all times due to the tail current source. With the time domain comparator proposed in Ref. [7], which just dissipates dynamic power, the SAR ADC is more effective and totally digitized. Meanwhile, other components of the SAR ADC are also enhanced to improve the total performance. For the DAC network, the layout standardization and compaction are vital to the circuit performance. Although the straightforward quadrate layout reduces the routing complexity, the common-centroid symmetry layout is ascendant in enhancing the linearity and diminishing the harmonic. By using the reset circuit in SAR control logic, the memory of comparator input is cleared and then the effect of anterior sample data is eliminated.

Founded on these aforesaid points, this paper presents a moderate sample speed and resolution SAR ADC which employs modified common-centroid symmetry layout, SAR reset circuit and time-domain comparator. Eventually, the SAR ADC shows lower power consumption and notable spurious-free dynamic range (SFDR).

2. ADC architecture

As depicted in Fig. 1, the typical 6-bit SAR ADC contains a sample and hold stage (S/H), a DAC achieved by binary-weighted capacitor array, a comparator and an SAR control logic^[8]. Its operating process is based on the conventional binary-search algorithm. The analog input signal is first sampled by the S/H, and then compared with the DAC's output. This procedure is controlled by SAR control logic. According to the comparison result, the digital output codes are generated sequentially.

3. Circuit implementation

3.1 DAC network

In a 6-bit SAR ADC, the DAC network usually adopts traditional binary weighted capacitor array. As shown in Fig. 2, given $C_{\rm o}$ as a unit capacitor, the network requires a total of 64$C_{\rm o}$. According to the control signal of SA algorithm, the capacitive DAC makes charge redistribution and generates the reference voltage through sample and hold stage. The redistribution result is based on Eq. (1). For 6-bit resolution, the least significant bit (LSB) is 15.625 mV, wherefore the circuit noise, calculated less than 10 $\times$ 10$^{-6}$ dimension, almost has no effect on the design performance.

In the DAC network, the matching accuracy of capacitor array is the key of engendering the spurious tone and influencing related parameters, such as dynamic range and linearity. In order to improve the matching accuracy, the layout of the capacitor array tends to be implemented with the common-centroid symmetry structure. Figure 3 shows a traditional common-centroid symmetry layout, in which the edge effect impacts DAC's accuracy. The larger capacitors suffer more from the edge effect, and thus the capacitors $C_{3}$, $C_{4}$, $C_{5}$ are more significant in determining the accuracy of DAC network. In Fig. 3, the edge ratio of capacitance $C_3$, $C_4$, $C_5$ is 8/32, 8/32, and 24/32, respectively. The difference among their edge ratios is 16/32. Consequently, an improved common-centroid symmetry layout^[9] is depicted for better matching in Fig. 4. In this layout structure, the edge ratio of capacitance $C_{3}$, $C_{4}$, $C_{5}$ is 16/32, 24/32, and 16/32, respectively. The difference among their edge ratios is 8/32, which is half of the traditional common-centroid symmetry layout.

For example, during the fourth time charge redistribution, the relationship of input voltage and charge redistribution result is calculated for the improved structure evaluation:

$\begin{align*} (64&+A_1+A_2+A_3)(V_{\rm CM}-V_{\rm IN})= \\[2mm] &(8+A_1)V_{\rm x}+(32+A_2)(V_{\rm X}-V_{\rm REF})+(16+A_3) \\[2mm] \;\;\;\;\;&\times\left(V_{\rm X}-\frac{1}{2}V_{\rm REF}\right)+8\left(V_{\rm X}-\frac{1}{4}V_{\rm REF}\right), \end{align*}$

(1)

where $A_1$, $A_2$, and $A_3$ are the edge ratio of capacitances $C_3$, $C_4$, and $C_5$, respectively. $V_{\rm CM}$ is the common-mode voltage, $V_{\rm IN}$ is the input voltage, $V_{\rm REF}$ is the reference voltage and $V_{\rm x}$ is the result of charge redistribution. Accordingly, the $V_{\rm x}$ is equal to

$\begin{equation} V_{\rm X}=V_{\rm CM}-V_{\rm IN}+\frac{42+A_2+\dfrac{1}{2}A_3}{64+A_1+A_2+A_3}V_{\rm REF}. \end{equation}$

(2)

The ideal result of charge redistribution $V_{\rm Xideal}$ is

$\begin{equation} V_{\rm Xideal}=V_{\rm CM}-V_{\rm IN}+\frac{42}{64}V_{\rm REF}. \end{equation}$

(3)

The difference between actual and ideal result, $\mathit{\Delta}_{\rm X}$, is

$\begin{equation} \mathit{\Delta}_{\rm X}=\frac{43+A_2+\dfrac{1}{2}A_3}{64+A_1+A_2+A_3}V_{\rm REF}-\frac{42}{64}V_{\rm REF}. \end{equation}$

(4)

For the traditional common-centroid symmetry layout where the $A_1$, $A_2$, and $A_3$ in Eq. (4) are 8/32, 8/32, and 24/32, respectively, the calculated $\mathit{\Delta}_{\rm X}$ is 0.0030$V_{\rm REF}$. On the other hand, the improved structure where the $A_1$, $A_2$, and $A_3$ in Eq. (4) are 16/32, 24/32, and 16/32, respectively, has a calculated $\mathit{\Delta}_{\rm X}$ of 0.0022$V_{\rm REF}$. The improved structure is closer to the ideal result, and its advantage is more prominent as the resolution increases. Meanwhile, the reduction of the edge effect keeps the DAC from the capacitor etching error which makes the capacitor constrict inwards, then makes the charge redistribution result incorrect. Equalizing the edge ratio of capacitance and improving the accuracy of DAC network, simultaneously, the complexity of this adopted capacitor array layout is acceptable. Furthermore, every unit capacitor has a circle of dummy capacitors for unanimous etch atmosphere.

For an $n$-bit ADC, the spurious-free dynamic range (SFDR) which is the ratio of the signal power and the largest spurious power is close to 9$n$ dB according to the following formula:

$\begin{equation} {\rm SFDR} \approx 9n-c\, ({\rm dB}), \end{equation}$

(5)

where the parameter $c$ is 0 for low resolution or 6 for high resolution^[10-12]. Accordingly the ideal SFDR of 6-bit SAR ADC is almost 54 dB. By using modified layout design which achieves better capacitor matching, the tested SFDR is 55.32 dB at 10 MHz sampling rate and 47.39-dB at 20 MHz sampling rate. The remarkable dynamic range leaves enough design margins for the RF transceiver front-end.

3.2 Time-domain comparator design

In conventional SAR ADC, the voltage-domain comparator is the only analog block and the foremost source of power consumption. In IEEE International Solid-State Circuits Conference (ISSCC) 2008, Reference [7] proposed the time-domain comparator which progressed fleetingly in the following years. An improved and power-efficient time-mode comparator proposed by Kobenge et al.^[13] is shown in Fig. 5. This comparator is differential, so the following analysis is done by the single-ended circuitry for illustration. While the comparator clock is low, transistor M5 turns on, then charges capacitor $C_{1}$ to supply voltage and resets the output nodes. Simultaneously, the residual charge of resistor $R_{1}$ is discharged through the path of transistor M1. When the signal clock is high, transistor M4 turns on and capacitor $C_{1}$ starts to discharge at a constant rate. Once the voltage of $C_{1}$ reaches the threshold of transistor M6, the following stage is triggered. The output of the comparator is based on discharging rate of the capacitor. Furthermore, a series of measures are adopted for reducing the power consumption. By employing a clocked inverter, transistor M9 turns off when the comparator works, which avoids the short circuit current. Referring to the feedback signal VINOFF, dynamic switch transistor M3 turns off when the comparison process is accomplished, which closes the discharging path and decreases energy.

3.3 SAR control logic

The successive approximation register logic is the scheduling block that supplies circuit control signals and guarantees the operation accuracy of DAC and comparator. In 6-bit 20 MHz synchronous SAR ADC, the clock frequency is 160 MHz according to the timing of synchronous SAR logic in Fig. 6. As disclosed in Fig. 7^{[14, 15]}, this block has two register rows, which involves the cyclic shift register in the top row and the DAC driving registers in the bottom row. Compared with the common synchronous SAR logic, a reset circuit is added in this design. After the last bit is completed, the reset circuit clears the memory of comparator input. This performance eliminates the effect of anterior sample data and achieves the 55.32 dB-SFDR at 10 MS/s with low input frequency and 47.39 dB-SFDR at 20 MS/s with Nyquist input frequency from the experimental results.

4. Measurement results

Fabricated in CMOS 0.18-$\mu$m technology with an active area of 0.98 mm$^{2}$, this ADC achieves a peak SFDR of 55.32 dB at 10 MS/s sampling rate. The die photograph is shown in Fig. 8. The static parameters, integral nonlinearity (INL) and differential nonlinearity (DNL) are measured with a low frequency and full swing sinusoidal input. As indicated in Fig. 9, the peak INL and DNL are less than 0.38/-0.81 LSB and 0.83/-0.77 LSB, respectively. The measured spectrum shown in Fig. 10 illustrates the dynamic measurement of 191.3 kHz and 4.9 MHz at 10 MS/s sampling rate. The ADC reaches 55.32-dB SFDR and 32.47-dB signal-to-noise and distortion ratio (SNDR) with 191.3 kHz input frequency. Figure 11 describes the SFDR and SNDR versus varying input frequency at 10 MS/s sampling rate. According to the measured result, the SFDR is still close to 45 dB at 4.9 MHz input signal. Moreover, the test result reveals that the ADC is still functioning well when the sampling rate increases to 20 MHz. Displayed in Fig. 12, when this ADC operates at 20 MS/s with a 9.3 MHz input tone, the SFDR and SNDR are 47.39 dB and 29.42 dB respectively and the effective number of bits (ENOB) is 4.6 bit. Including the output buffer and input and output (I/O) pad, the ADC consumes 522 $\mu$W at 1.8 V supply, corresponding to a figure of merit (FOM) of 1.5 pJ/step. The calculation of FOM^[16] which assesses the efficiency of the ADC is based on the typical definition which is defined as:

$\begin{equation} {\rm FOM}=\frac{\rm Power}{2^{\rm ENOB} f_{\rm s}}. \end{equation}$

(6)

The fabricated SAR ADC is mounted on a custom four-layer printed circuit board (PCB), and a photograph of the test environment^{[9, 17]} is depicted in Fig. 13. The Agilent E3631A supplies the chip power, and the analog and digital power voltages are divided to avoid the mutual interference. The Agilent N9310A and E4438C produce a sine wave input signal and clock signal, respectively. While the input frequency is close to Nyquist frequency, a low pass filter is employed to strain off harmonic waves. The Agilent logic analyzer 16823A collects the output codes which are analyzed and calculated by MATLAB software.

Table 1 compares our proposed ADC with other 6-bit SAR ADCs and summarizes its performance. This design achieves prominent SFDR using synchronous timing logic with 0.18 $\mu$m technology. For 6-bit SAR ADC, this design is the only one in recent years that achieves an SFDR over 55 dB and one of only a few ADCs that reach 5.1-bit ENOB^[18]. Furthermore, the ADC's INL and DNL are both less than 1 LSB, which satisfies the demands for various application areas. From the contrast, the national performance has a great distance to catch up with the international leading edge. Our universities and research institutions have focused on the low resolution and high speed field in recent years. However, our design goal is to meet the request of radio-frequency (RF) transceiver front-end for the WSN application, where a 6-bit 20-MS/s ADC is sufficient and the 0.18-$\mu$m 1P6M CMOS technology is more economical. The future work includes an advanced process, novel design thought, and a high function test instrument to achieve higher speed and spurious-free dynamic range for more extensive applications.

5. Conclusion

In this paper, a synchronous and single-ended 6-bit 20-MS/s SAR ADC is accomplished in 0.18-$\mu$m CMOS technology. Adopting the common-centroid symmetry layout and modified synchronous SAR control logic, this proposed ADC achieves 55.32 dB-SFDR and 5.1 bit-ENOB at 10 MHz sampling rate. Additionally, it reaches 47.39 dB-SFDR and 4.6 bit-ENOB at 20 MHz sampling rate. Relying on time-mode comparator, the power consumption is 522 $\mu$W, which is comparatively lower than the SAR ADC based on a traditional voltage comparator.