1. Introduction

Along with the development of integrated circuit (IC) technology, more and more functions are able to be integrated in a single chip, termed system on a chip (SoC). In an SoC, analog circuits are normally compliant with digital circuits in terms of manufacturing process, and therefore some analog architectures which are suitable for scaling become more popular. Taking analog-to-digital converters (ADCs) as an example, among different topologies of data converters, the successive approximation register (SAR) ADC with its advantage of low power, is well compatible with advanced processes because it has no other active analog circuits and only one comparator. Thanks to new switching schemes and faster processes, SAR ADCs have achieved several tens of, MS/s to low GS/s sampling rates with 5-bit to 10-bit resolutions, which are necessary building blocks for 802.11/a/b/g wireless networks, digital TV applications, and mobile applications, such as DVB-T, DVB-H, and TDMB^[1-3]. In battery-powered SoC applications, SAR ADCs are widely adopted for their high power efficiency. Another feature of an ADC is that its sampling frequency can be adjusted for different applications.

2. ADC architecture and function

Figure 1 shows the architecture of the 10-bit SAR ADC. It is comprised of differential capacitor arrays, a dynamic latch comparator with a special preceding source-follower and SAR logic with a high-speed clock inside. The capacitor array functions as a 9-bit DAC (digital to analog converter), which generates the required voltages for comparison. A differential structure is applied to overcome the non-ideal effects of the switched capacitor circuit. A latch structure is widely used in SAR ADC comparators for its high speed. The special source-follower is proposed to diminish the leakage current. SAR logic requires a clock with at least ten times the sampling clock frequency and a tunable high speed clock generator is implemented. Detailed information about the circuit design will be described in the following sections and this section focuses on the function of the SAR ADC.

The fact, that SAR ADC can achieve more than 10 MS/s sampling rate nowadays, mainly owing to the possibility of using small total capacitance and the speed benefit from the advanced technology. As we know, the most time-consuming part of a whole SAR conversion is the settling time taken by the inner DAC. As the settling time is proportional to time constant, the smaller the total capacitance, the faster speed the SAR ADC can achieve. Further, smaller total capacitance also leads to less energy being stored on the capacitive array. Therefore, a small total capacitance is of great importance for high speed and low power SAR ADCs. Two techniques are used in this design to obtain small total capacitance, the top-plate-sample switching scheme and the split capacitor structure.

Reference [2] did an excellent job with the top-plate-sample switching procedure. Rather than using a split capacitor structure, it obtained small total capacitance by making use of three metal layers to create only a 4.8 fF unit capacitor ($C_{\rm u})$. Compared with the conventional switching method^[4], the top-plate-sample switching procedure has relatively higher energy efficiency. Once the comparison finishes, the top-plate-sample scheme has a definite decision to switch for the next comparison. It has no "up" transition power cost, while the conventional switching scheme needs test to make decision^[5].

The split structure with the unit bridge capacitor ($C_{\rm bridge}$ $=$ $C_{\rm u})$ significantly reduces total capacitance^[6]. In this design, the 10-bit SAR ADC has total capacitance of 720 fF with 22.5 fF $C_{\rm u}$. The cost is the high sensitivity to parasitic capacitance, especially for the parasitic capacitance of the top plate of the bridge capacitor to ground. To diminish this parasitic effect, the three-row layout is implemented and will be described in Section 3.

2.1 Switching scheme

Figure 2 shows the voltage change of the capacitive arrays in a cycle, which helps to understand how the ADC works. During the sampling phase, sampling switches $S_{\rm 0p}$ and $S_{\rm 0n}$ are turned on and all the other switches are connected to $V_{\rm cm}$. In this way, the differential analog signal is stored on the differential capacitive arrays, which is

$$\begin{equation} \label{eq1} v_{\rm p0}-v_{\rm n0}=v_{\rm in}. \end{equation}$$

(1)

Then sampling switches $S_{\rm 0p}$ and $S_{\rm 0n}$ are turned off and the charge on the top plates of the capacitive arrays is conserved. Nine conversion phases follow, which include ten comparisons and nine charge redistributions. Charge redistribution changes the voltages on the top plates of the two capacitive arrays. The general recursive expression of the two capacitive arrays differential voltage is:

$$\begin{equation} \label{eq2} v_{{\rm pn}i}=v_{{\rm p}i}-v_{{\rm n}i}=v_{{\rm pn}(i-1)}-b_{(i-1)}\times \frac{2^{9-i}}{511}\times (v_{\rm ref+}-v_{\rm ref-}), \end{equation}$$

(2)

where the bit comparing result is

$b_i=\begin{cases} 1, \quad v_{{\rm p}i}>v_{{\rm n}i}, \\[2mm] -1, \quad v_{{\rm p}i}< v_{{\rm n}i}. \end{cases}$

Equations (2) are derived from Eqs. (4) and (5) presented in Section 3 with $C_{\rm parasitic}$ $=$ 0.

The ADC converts analog signal ranging from $V_{\rm ref-}$–$V_{\rm ref+}$ to $V_{\rm ref+}$–$V_{\rm ref-}$ to ten digital bits with quantization error no larger than $\frac{1}{2^9 -1} (V_{\rm ref+}-V_{\rm ref-})$.

2.2 Timing strategy

More details about the timing strategy of the ADC are illustrated in Fig. 3. As shown in the upper part of Fig. 3, there are nine equal conversion phases (cnv1 to cnv9) and one sample phase in each cycle. The sampling clock (sampleclk) is frequency-fixed and provided outside the chip, while the oscillating clock (selfclk) is generated inside the chip and its frequency can be adjusted. The positive edge of "sampleclk" ends the sample phase and starts the conversion phase. After nine equal conversion phases, the tunable clock generator (selfclk) stops oscillating and the rest time of this cycle is for the sample phase. As the cycle is determined by the "sampleclk" which is fixed, the sum of nine conversion phases and sample phase is constant. Therefore the time distribution between the conversion phases and the sample phase can be controlled by adjusting the "selfclk" frequency. The faster the "selfclk" is, the longer the sample phase is.

During each conversion phase, several actions are operated one by one shown in the lower part of Fig. 3. Firstly, the rising edge of "selfclk" triggers the start of comparison (strobe). When the comparison is finished (take $t_{\rm latch}$ time), the comparison result is locked and a flag signal (cmp{\_}done) is generated by the comparator. This signal then triggers the control logic. After some logical and buffering delay ($t_{\rm logic})$, the capacitive array begins to redistribute charge and prepare voltage for the next comparison. This charge redistribution action lasts till the end of this conversion phase ($t_{\rm CapArray})$.

The frequency of "selfclk" can be used to adjust the time distribution between the conversion phases and the sample phase, so can the duty cycle of "selfclk". The falling edge of "selfclk" triggers the preamplifier (pre-amp) in the comparator to turn from reset stage (reset) to release stage (release). So the lengths of the two stages of the preamplifier can be adjusted by the duty cycle of "selfclk".

3. Parasitic analysis in 9-bit DAC

3.1 Parasitic capacitance

The 10-bit SAR ADC needs a 9-bit DAC to generate voltage to compare. Usually a capacitor array is a reasonable choice for medium resolution and high-speed applications. Instead of using a binary weighted structure, a split capacitive array is adopted in this design to achieve small total capacitance, which is shown in Fig. 4.

The biggest feature of the split structure is that a bridge capacitor $C_{\rm bridge}$ is inserted between two conventional binary weighted capacitor arrays. As the higher side and the lower side are naturally binary weighted, the whole capacitive array is binary weighted if only $C_{\rm 1H}$ and $C_{\rm 8L}$ are binary weighted. This condition can be satisfied by assigning one $C_{\rm u}$ to $C_{\rm bridge}$ and assigning $i$ times $C_{\rm u}$ to $C_{\rm iH}$ or $C_{\rm iL}$. However, the capacitance-save split structure has the cost that the capacitive DAC is highly sensitive to parasitic capacitor, especially for the parasitic capacitor of the top plate of the lower 4-bit side to ground ($C_{\rm parasitic})$. To quantitatively analyze the parasitic effect, $C_{\rm iL}$ and $C_{\rm iH}$'s voltage contribution on the top plate of the higher 5-bit side is calculated.

When a switch for $C_{\rm iL}$ turns from $V_{\rm cm}$ to VDD or VSS, the voltage change on the top plate of the lower 4-bit side can be calculated as

$$\begin{equation} \begin{split} \label{eq3} \Delta V_{\rm LOWER \_TOP\_CiL} ={}& C_{\rm iL} \Bigg[\sum\limits_{k=1}^4 C2^{k-1}L +\sum\limits_{k=1}^5 C2^{k-1}H C_{\rm bridge}\\[2mm] &{}\times \Bigg(\sum\limits_{k=1}^5 C2^{k-1}H+ C_{\rm bridge}\Bigg)^{-1}\\[2mm] &{}+C_{\rm parasitic}\Bigg]^{-1} \Delta V. \end{split} \end{equation}$$

(3)

Thus, the voltage change on the top plate of the higher 5-bit side is

$$\begin{equation} \begin{split} \Delta V_{\rm HIGHER\_TOP\_CiL}{}& =\frac{C_{\rm bridge}}{\sum\limits_{k=1}^5 {C2^{k-1}H} +C_{\rm bridge}} \\[3mm]& \quad \times \Delta V_{\rm LOWER\_TOP\_CiL} \\[2mm]& =\frac{i C_{\rm u}}{511 C_{\rm u}+32 C_{\rm parasitic}} \Delta V. \end{split} \end{equation}$$

(4)

Similarly, when a switch for $C_{\rm iH}$ turns from $V_{\rm cm}$ to VDD or VSS, the voltage change on the higher 5-bit top plate is

$$\begin{equation} \begin{split} \Delta V_{\rm HIGHER\_TOP\_CiH} {}& =C_{\rm iH} \left[ \sum\limits_{k=1}^5 {C2^{k-1}H}\right. \\[2mm]& \left. +\frac{\left(\sum\limits_{k=1}^4 C2^{k-1}L+C_{\rm parasitic}\right) C_{\rm bridge}} {\left(\sum\limits_{k=1}^4 C2^{k-1}L+C_{\rm parasitic}\right)+ C_{\rm bridge}} \right] \Delta V \\[4mm]& =\frac{i (16 C_{\rm u}+C_{\rm parasitic})}{511 C_{\rm u}+32 C_{\rm parasitic}} \Delta V. \end{split} \end{equation}$$

(5)

When $C_{\rm parasitic}$ $=$ 0, we can achieve from Eqs. (4) and (5) that the weight of $C_{\rm 1H}$ and the weight of $C_{\rm 8L}$ are 16/511 and 8/511, respectively. From the previous analysis, the whole split structure are binary weighted in the ideal case. Considering $C_{\rm parasitic}$, we find that $\Delta V_{\rm HIGHER\_TOP}$ and $i$ still have linear relationship in Eqs. (4) and (5). This means that $C_{\rm parasitic}$ does not affect the linearity of the two sub-arrays divided by the $C_{\rm bridge}$. $C_{\rm parasitic}$'s effect on the two separate sides can be regarded as gain errors. However, the gain errors of the two binary weighted arrays are not the same. This results in different gains between the two separate sides.

To fairly compare the two gains, the gain of $C_{\rm iL}$ should times sixteen to have the same weight with $C_{\rm iH}$. From Eqs. (4) and (5) we can achieve that the gain ratio is

$$\begin{equation} \label{eq6} \frac{16 \Delta V_{\rm HIGHER\_TOP\_CiL}} {\Delta V_{\rm HIGHER\_TOP\_CiH}}= \frac{16 C_{\rm u}}{16 C_{\rm u}+C_{\rm parasitic}}<1. \end{equation}$$

(6)

The gain difference leads to a large DNL (differential nonlinearity) error between every "xxxxx1111" and "xxxxx0000". Figure 5 illustrates such $C_{\rm parasitic}$ effect on the DNL in a 4-bit 2-2-split DAC as an example. As the lower side gain is smaller than the higher side gain, the DNL does not result in missing code. The largest DNL caused by $C_{\rm parasitic}$ can be calculated,

$$\begin{equation} \label{eq7} {\rm LSB}=\frac{\sum\limits_{j=1}^5 {\Delta V_{\rm HIGHER\_TOP\_C2}^{j-1}H} +\sum\limits_{j=1}^4 {\Delta V_{\rm HIGHER\_TOP\_C2}^{j-1}L} }{511}, \end{equation}$$

(7)

$$\begin{equation} \begin{split} {\rm DNL}_{{\rm max}\_C_{\rm parasitic}} ={}&\Big( \Delta V_{\rm HIGHER\_TOP\_C1H}-\sum\limits_{j=1}^4 \Delta V_{\rm HIGHER\_TOP\_C2}^{j-1}L \\[2mm]& -{\rm LSB}\Big)/ {\rm LSB} \\[2mm] ={}&\frac{480 C_{\rm parasitic}}{511 C_{\rm u}+31 C_{\rm parasitic}}. \end{split} \end{equation}$$

(8)

From Eq. (8), small $C_{\rm parasitic}$ leads to small DNL$_{\rm max}$, which is the inspiration for how the three-line layout method is designed. The conventional common-centroid layout method is not suitable for the split structure, because the common top plate connection is so complex that the metal-connection parasitic capacitance to ground ($C_{\rm parasitic})$ is large enough to ruin the static and dynamic performance.

The three-row layout method successfully eases the connection complexity, which makes the key parasitic capacitance very small. In this design, each capacitive array consists of three capacitor rows, and each row contains 35 unit capacitors (Fig. 6). Three rows from the top down correspond to lower 4 bits, the bridge capacitor and higher 5 bits (Fig. 4), which employ 15, 1, and 31 unit capacitors, respectively. At each row, the used unit capacitors are symmetrically distributed in the middle, while the redundant unit capacitors are used as dummies and distributed on two sides. In this way, the connection of the common top plate is short and the key parasitic capacitance to ground ($C_{\rm parasitic})$ is less than 6 fF (DNL$_{{\rm max}{\_}C_{\rm parasitic}}$ $=$ 0.25 LSB calculated from Eq. (8) with $C_{\rm u}$ $=$ 22.5 fF and $C_{\rm parasitic}$ $=$ 6 fF) evaluated by post simulation.

However, the measurement DNL$_{\rm max}$ (ADC DNL but with strong split structure character) is worse than the evaluation. The main cause is the $C_{\rm bridge}$ mismatch, which results in gain difference between the two sub-arrays similar with $C_{\rm parasitic}$. As the $C_{\rm bridge}$ can be adjusted, we can use this character to calibrate the nonlinearity caused by the split structure. For quantitative analysis, assign $C_{\rm u}+\Delta C_{\rm bridge}$ to $C_{\rm bridge}$ and ideal values to other capacitors, the gain ratio of the two separate sub-arrays including $\Delta C_{\rm bridge}$ and $C_{\rm parasitic}$ is,

$$\begin{multline} \frac{16 \Delta V_{\rm HIGHER\_TOP\_CiL}}{\Delta V_{\rm HIGHER\_TOP\_CiH}} \\[2mm] =\frac{16 (C_{\rm u}+\Delta C_{\rm bridge})} {16 C_{\rm u}+C_{\rm parasitic}+\Delta C_{\rm bridge}}=1, \\[2mm] {\rm if}\; \Delta C_{\rm bridge}=\frac{C_{\rm parasitic}}{15}. \end{multline}$$

(9)

From Eq. (9), the nonlinearity is able to be calibrated if $\Delta C_{\rm bridge}=\frac{C_{\rm parasitic}}{15}$.

3.2 Parasitic resistance

The charge redistribution time is critical for a high speed SAR ADC. As the higher bits have larger voltage to settle, the higher the bit is, the stricter its requirement is. To simply the analysis, the bridge capacitor and the lower 4-bit side are modeled as a $C_{\rm u}$ in series with a unit resistor ($R_{\rm u})$, which is shown in Fig. 7. More accurate calculation shows that the practical case is more optimistic than this simplification. $V_{\rm x}$ in Fig. 7 represents reference voltage, which may be $V_{\rm ref+}$, $V_{\rm ref-}$ or $V_{\rm cm}$. The bottom ends of different branches may be connected to different reference voltages at the same moment, so a dashed line is drawn instead. In this design, analog source and ground (VDD and VSS) are adopted as $V_{\rm ref+}$ and $V_{\rm ref-}$. Their parasitic resistance is negligible by careful layout, which is also the requirement for low source voltage drop. $V_{\rm cm}$ is achieved by half dividing VDD with two resistors outside the chip. As a large capacitor is shunted with $V_{\rm cm}$, it can be regarded as an ideal voltage source in this analysis as well as $V_{\rm ref+}$ and $V_{\rm ref-}$. The parasitic resistance considered here is switch average-on-resistance.

The sampling switch uses the bootstrapping technique and others are common MOS switches. The on-resistance of each MOS switch is carefully designed and follows the next principle. The principle is that the product of $R_{\rm on}$ and $C_{\rm branch}$ is equal to the product of $R_{\rm u}$ and $C_{\rm u}$, which is achieved by scaling the transistor width. Following this principle, the nodes between $C_{\rm branch}$ and the switches have the same electrical potential if only the bottom ends of their branches are connected together. Shorting nodes with the same electrical potential does not change the electrical character. This skill eases the calculation when obtaining the AC (alternating current) equivalent circuit during the sample phase and the conversion phase.

During the sample phase, the input signal is sampled onto the capacitive array through $R_{\rm sample}$ and all the MOS switches are connected to $V_{\rm cm}$ (regarded as AC ground). The time constant is

$$\begin{equation} \label{eq10} \tau_{\rm sample}=\left(R_{\rm sample}+\frac{R_{\rm u}}{32}\right)\times 32C_{\rm u}=R_{\rm sample} C_{\rm total}+R_{\rm u} C_{\rm u}. \end{equation}$$

(10)

During the conversion phase, the sample switch is turned off. And one branch with the weight of x changes its bottom-plate voltage from $V_{\rm cm}$ to one of the reference voltages ($V_{\rm ref+}$ or $V_{\rm ref+})$ while the other branches remain unchanged (regarded as AC ground). The time constant is

$$\begin{equation} \label{eq11} \tau_{\rm conversion}=\left(\frac{R_{\rm u}}{x}+\frac{R_{\rm u}}{32-x}\right) \frac{xC_{\rm u} (32-x)C_{\rm u}}{xC_{\rm u}+(32-x)C_{\rm u}}=R_{\rm u} C_{\rm u}. \end{equation}$$

(11)

From Eq. (11) we can see that all the branches have the same $\tau_{\rm conversion}$. Equation (10) shows that $\tau_{\rm sample}$ is larger than $\tau_{\rm conversion}$ and mainly depends on $R_{\rm sample}$ and $C_{\rm total}$.

The phase time should be long enough to make sure that the dynamic error is smaller than one LSB,

$$\begin{equation} \label{eq12} {\rm error}_{\rm dynamic} =V_{\rm transfer} \exp \left(-\frac{T_{\rm phase}}{\tau_{\rm phase}}\right) <1, {\rm LSB}, \end{equation}$$

(12)

where $V_{\rm transfer}$ is the DAC transferring voltage, $T_{\rm phase}$ and $\tau_{\rm phase}$ represent the time and time constant of sample phase or conversion phase. Equation (12) along with $C_{\rm parasitic}$ and capacitor mismatch together determine the minimum $C_{\rm u}$. Information about capacitor mismatch standard variance $\sigma$ can be looked up in the PDK file. A MATLAB model is written to estimate the distortion caused by $C_{\rm parasitic}$ and capacitor mismatch in this design. Further, for a 10-bit resolution ADC with 1-V supply, noise is the secondarily significant distortion factor.

4. The proposed comparator

Figure 8 shows the schematic of the proposed comparator. The comparator is comprised of four parts, an anti-leakage source follower, a preamplifier, a dynamic latch and an SR latch to lock the comparing result. The source follower in the first stage, whose gain is smaller than 1, seems to make no sense here, because the less-than-1 gain cannot help reduce offset but lowers speed and adds additional current. The key lies in the differential input MOS transistors of the first stage, which are native 2.5 V transistors. They are designed to eliminate the gate leakage current of the comparator.

4.1 Overcome leakage current

The total 720 fF capacitive array is sensitive to charge leakage, and a 115.2 nA leakage current can result in one LSB voltage drop. As shown in Fig. 1, the differential input transistors of the comparator are connected to the capacitive arrays and charge can leak out through the transistor gate. The standard transistor in the 65 nm GP process has more than 100 nA leakage current in extreme corner and temperature for its ultra-thin gate oxide, so the 2.5 V IO transistor with a thick gate oxide is a good choice. However, there comes another problem that the IO transistor has higher than 0.7 V threshold voltage and the 0 V to 1 V range input cannot guarantee to turn it on. Finally a pair of native 2.5 V IO transistors is used to form a pseudo differential input stage of the comparator.

Another current leakage source is the channel leakage current of the bootstrap switch, which is not that serious and is diminished to an endurance amount by using high threshold voltage transistors in place of standard transistors.

4.2 Meta-stability

All latching comparators have the problem of meta-stability. The comparator speed requirement for the meta-stability effect can be calculated by the following simple model in Fig. 9.

From the model we can achieve the following expressions,

$$\begin{equation} \label{eq13} i=C\frac{{\rm d}v}{{\rm d}t}=\frac{(A-1)v}{R}, \end{equation}$$

(13)

$$\begin{equation} \label{eq14} v=v_0\exp \frac{(A-1)t}{\tau}, \end{equation}$$

(14)

where $v$ is the output voltage, $v_{0}$ is the initial starting state for regeneration, $A$ is the latching gain and $\tau$ is the time constant (in this case is RC).

In the SAR ADC timing strategy, output voltage $v$ has to reach the logic turning point $V_{\rm logic\_trig}$ within the maximum comparing time $T_{\rm compare\_max}$. So from Eq. (14) we can obtain the smallest starting regeneration value $V_{\rm ini\_min}$, which should be much smaller than one LSB.

$$\begin{equation} \label{eq15} V_{\rm ini\_mim}=V_{\rm logic\_trig} \exp \left[-\frac{(A-1)T_{\rm compare\_max}}{\tau} \right] \ll 1, {\rm LSB}. \end{equation}$$

(15)

The actual comparator behavior is much more complicated. Three operation phases can be divided^[7]. Usually, the last phase during which only the cross-coupled inverters M10–13 are active takes most of the time and performs as the simple latching model. The actual time constant of the comparator can be achieved by simulation. In our design, the 65 nm GP process provides a rather fast comparator and Equation (15) can be easily satisfied.

However, no matter how fast the comparator is, it always has the possibility of taking more than $T_{\rm compare\_max}$ time to generate the result. Though the comparing result itself hardly affects the ADC performance (if Equation (15) is satisfied), the long decision time is able to ruin the SAR timing and logic. This is one of the reasons that cause the measurement performance of the ADC to be lower than expected. A good solution is that when the comparator takes longer time than $T_{\rm compare\_max}$ to decide, the logic is forced to enter the next stage and whether fixed "1" or fixed "0" is taken as the comparing result with negligible influence.

5. SAR logic and clock

Comparing to conventional SAR logic, a flip-flop delay is saved by making better use of the logical information. Another important part of the SAR logic is the inner ultra-high speed clock (selfclk). As there is no PLL (phase locking loop) provided inside the chip, a tunable clock generator is designed.

5.1 Critical path optimization

A small logical optimization is depicted in Fig. 10. The arc in the upper circuits shows the data critical path in the conventional SAR logic. By making further use of the "begin" signal information, the lower circuits are implemented with a one-OR-and-one-"D flip–flop"-long data path. For stage i, the OR result of “begin <i>” and "cmp_done" triggers “D <i>”. As “begin <i>” lasts high once "start" passed by, the OR result remains high and “D <i>” will not be disturbed by the next "cmp_done" rising edges. At the same time, “begin<i+1>” is sent to reset “D <i>”, which guarantees that no "cmp_done" rising edge can trigger “D <i>” until "start" has passed by “DB<i+1>” (“begin<i+1>” remains high). The critical path is relaxed for one flip-flop delay. But given that this logical delay will repeat 9 times, so every tiny improvement makes a small contribution to speeding up the conversion. Besides, buffering should be paid attention as the scaling process leads to a smaller buffer capability. The buffering time cost on a wire-to-wire parasitic capacitor is almost as long as the logical delay time.

5.2 Tunable high speed clock generator

The schematic in Fig. 11 is the tunable clock generator used in the design. M1–M9 mirrors the current $I_{\rm bias}$. M10–M15 are used to decide whether their corresponding branch circuits on or off. If the PMOS branch is on, $C_1$ is charged; otherwise if NMOS branch is on, $C_1$ is discharged. Apparently PMOS and NMOS branches cannot be turned on at the same time. M16–M21 form a Schmitt trigger providing an appropriate voltage range. $C_1$ and "selfclk" have opposite voltage levels. When $C_1$ is higher than the Schmitt trigger turning point, the "selfclk" turns low, then "selfclk" turns the NMOS branch on to discharge $C_1$ through logic circuits. Similarly when $C_1$ is low enough, then the "selfclk" turns high, and the PMOS branch is turned on to charge $C_1$. In this way, a stable oscillation is generated. The clock frequency can be adjusted by $I_{\rm bias}$ and M10–M15, and M10–M15 can adjust the clock duty cycle as well.

6. Measurement results

The prototype was fabricated using 1P9M (one-poly-nine-metal) 65 nm GP CMOS technology. The full micrograph of the core is shown in Fig. 12. The total core area of the chip is 0.13 mm$^{2}$.

Figure 13 shows the ADC output spectrum with the input frequency at 1.8 MHz under 80 MS/s sampling rate. The dynamic performance of the ADC is shown in Fig. 14 with sampling frequency sweeping from 10 to 85 MHz. The measured DNL and INL are shown in Fig. 15. All the measured performance results are summarized in Table 1 and Table 2 shows the comparison between the proposed ADC and previous work. From Table 2 we can see that this paper achieves the highest sampling speed among the comparative literature. Its power efficiency is much higher than the pipelined ADC with a similar spec and the SAR ADC in low speed. The state-of-the-art work^[11] benefits from the SOI process while this design overcomes the new problems resulting from the ultra-deep sub-micron standard CMOS process, which has an urgent need in communicating and consumer electronics application. Reasons and improvement solutions to the relatively lower SINAD are presented in Section 7.

7. Improvement solutions

In this section, the main reasons for the relatively lower SINAD are summarized and feasible improvement solutions are provided.

7.1 Bonding wire and reference oscillation

The DAC in the 10-bit 80-MS/s SAR ADC works in more than 800 MHz frequency, so its two references $V_{\rm ref+}$ and $V_{\rm ref-}$ have to have a wide-GBW (gain bandwidth product) buffer to guarantee the settling error to be small enough. If they are provided inside the chip, the reference buffer will probably cause more power than the SAR ADC itself. In order to achieve an ultra-low power ADC chip, the references in this design are taken directly from the analog source and ground. However, the parasitic inductor of the bonding wire and the decouple capacitor connected between the analog source and ground cause oscillation and thus affect the charge redistribution operation.

Figure 16 illustrates the circuit model. $I_{\rm in}$(s) models the capacitive array, which acts like a current impulse. $R_{\rm deglitch}$ helps solve the oscillation problem, but is not included in this design. $V_{\rm out}(s)$ is the achieved reference voltage inside the chip. Seeing from the arrow direction, we can obtain the transfer function $H(s)$ $=$ $V_{\rm out}(s)/I_{\rm in}(s)$ and its impulse response simulated in MATLAB is shown in Fig. 17. The amplitude in Fig. 17 is so large because of the infinitely high peak of the impulse input. Practical $I_{\rm in}(s)$ has a constant integral (constant redistribution charge) like impulse input but with a finite peak. The impulse response just explains the principle and more accurate results can be achieved by circuit simulation. In the upper subfigure 17, if the $R_{\rm deglitch}$ is not inserted, an amount of charge injection will cause $L_{\rm bonding}$ and $C_{\rm decouple}$ to oscillate and its oscillation amplitude hardly attenuates at the comparison moment. This affects the ($V_{\rm ref+}$ – $V_{\rm ref-})$ in Eq. (2) and thus possibly leads to a wrong comparing result. It mainly accounts for the numerous harmonics in Fig. 13. If an around 15 $\Omega$ $R_{\rm deglitch}$ is inserted in the lower subfigure 17, it will quickly attenuate the oscillation amplitude. If the amplitude is attenuated into much smaller than 1 LSB degree within the charge redistribution phase, the oscillation effect will be eliminated. This solution is proven by measurement in the next tapeout version with the same situation.

7.2 The DAC and comparator's non-ideal effect

An obvious observation of the INL diagram in Fig. 15 is that it has 32 regular slopes. Careful analysis finds that all of, the 32 slopes fall between the bit "xxxxx1111" and "xxxxx0000". This is a strong evidence for split-structure distortion. Based on the analysis in Section 3.1, the distortion is mainly caused by parasitic capacitance and bridge capacitor mismatch. Because of the high sensitivity of the structure and the randomness of mismatch, calibration is a necessity to achieve 10-bit resolution using a split structure. The calibration can be implemented by adjusting the $C_{\rm bridge}$ and $C_{\rm parasitic}$.

The comparator meta-stability mentioned in Section 4.2 is also a factor that affects measurement results. Another significant factor of the comparator is mismatch. Its statistic mismatch causes ADC offset, while its dynamic mismatch leads to ADC distortion. Similar to the DAC, the comparator mismatch needs to be calibrated as well.

8. Conclusion

A 10-bit 80-MS/s reference-free PLL-free SAR ADC for communication and consumer electronics application is presented. The top-plate sampling scheme and the split capacitive structure lead to a small total capacitance of 720 fF. All of the design is in 1-V supply and special transistors are chosen to overcome the charge leakage of the 65 nm GP process. Without using a PLL, a tunable high-speed clock generator is implemented. The prototype ADC occupies an active area of 0.13 mm$^{2}$. When operating at 80 MS/s, this design draws total 1.6 mW power and obtains a power efficiency of, 94.8 fJ/conv-step.