J. Semicond. > 2013, Volume 34 > Issue 8 > 085016

SEMICONDUCTOR INTEGRATED CIRCUITS

A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

Ye Han, Quanliang Li, Cong Shi and Nanjian Wu

+ Author Affiliations

 Corresponding author: Wu Nanjian, Email:nanjian@semi.ac.cn

DOI: 10.1088/1674-4926/34/8/085016

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Abstract: This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

Key words: CMOS image sensorcolumn-parallel cyclic ADCcorrelated double samplingoffset cancellation



[1]
Yang D, Fowler B, Gamal A. A Nyquist-rate pixel-level ADC for CMOS image sensors. IEEE J Solid-State Circuits, 1999, 34(3):348 doi: 10.1109/4.748186
[2]
Watabe T, Kitamura K, Sawamoto T, et al. A 33 M pixel 120 fps CMOS image sensor using 12 b column-parallel pipelined cyclic ADCs. IEEE International Solid-State Circuits Conference, 2012:388
[3]
Kleinfelder S, Lim S, Liu X, et al. A 10000 frames/s CMOS digital pixel sensor. IEEE J Solid-State Circuits, 2001, 36(12):2049 doi: 10.1109/4.972156
[4]
Krymski A I, Tu N. A 9-V/lux-s 5000-frames/s 512×512 CMOS sensor. IEEE Trans Electron Devices, 2003, 50(1):136 doi: 10.1109/TED.2002.806958
[5]
Oike Y, Gamal A E. A 256×256 CMOS image sensor with Σδ-based single-shot compressed sensing. IEEE International Solid-State Circuits Conference, 2012:386
[6]
Furuta M, Nishikawa Y, Inoue T, et al. A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters. IEEE J Solid-State Circuits, 2007, 42(4):766 doi: 10.1109/JSSC.2007.891655
[7]
Park J H, Aoyama S, Watanabe T, et al. A high-speed low-noise CMOS image sensor with 13-b column-parallel single-ended cyclic ADCs. IEEE Trans Electron Devices, 2009, 56(11):2414 doi: 10.1109/TED.2009.2030635
[8]
Razavi B. Design of analog CMOS integrated circuits. New York: McGraw-Hill, 2001
[9]
Hwang K. Computer arithmetic principles, architecture and design. New York: John Wiley & Sons, 1979
[10]
Andrew A, Paul G. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits, 1999, 34(5):599 doi: 10.1109/4.760369
[11]
Bigas M, Cabrujaa E, Forest J, et al. Review of CMOS image sensors. Solid-State Electron, 2006, 37:433
[12]
Theuwissen J, Albert P. CMOS image sensors:state-of-the-art. Solid-State Electron, 2008, 52:1401 doi: 10.1016/j.sse.2008.04.012
[13]
Zhang Na. Research on key techniques of super high speed digital CMOS image sensor. Dissertation for the Doctoral Degree, Tianjin: Tianjin University, 2008(in Chinese)
Fig. 1.  Block diagram of the cyclic ADC.

Fig. 2.  Schematic of the sub-ADC.

Fig. 3.  Schematic of the comparator.

Fig. 4.  Schematic of the MDAC.

Fig. 5.  Timing chart of the cyclic ADC.

Fig. 6.  Equivalent circuits of the noise canceling phase. (a) Step A. (b) Step B.

中文注解


Fig. 7.  Transfer function of the 1.5-bit architecture.

Fig. 8.  Equivalent circuits of the cyclic converting phase. (a) $\Phi_{1}$ (Odd phase). (b) $\Phi_{2}$ (Even phase).

Fig. 9.  Shift register and operation of the DEC.

Fig. 10.  Chip micrograph.

Fig. 11.  Measured DNL and INL.

Fig. 12.  Images taken by the sensor.

Table 1.   ADC performance summary and comparison.

[1]
Yang D, Fowler B, Gamal A. A Nyquist-rate pixel-level ADC for CMOS image sensors. IEEE J Solid-State Circuits, 1999, 34(3):348 doi: 10.1109/4.748186
[2]
Watabe T, Kitamura K, Sawamoto T, et al. A 33 M pixel 120 fps CMOS image sensor using 12 b column-parallel pipelined cyclic ADCs. IEEE International Solid-State Circuits Conference, 2012:388
[3]
Kleinfelder S, Lim S, Liu X, et al. A 10000 frames/s CMOS digital pixel sensor. IEEE J Solid-State Circuits, 2001, 36(12):2049 doi: 10.1109/4.972156
[4]
Krymski A I, Tu N. A 9-V/lux-s 5000-frames/s 512×512 CMOS sensor. IEEE Trans Electron Devices, 2003, 50(1):136 doi: 10.1109/TED.2002.806958
[5]
Oike Y, Gamal A E. A 256×256 CMOS image sensor with Σδ-based single-shot compressed sensing. IEEE International Solid-State Circuits Conference, 2012:386
[6]
Furuta M, Nishikawa Y, Inoue T, et al. A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters. IEEE J Solid-State Circuits, 2007, 42(4):766 doi: 10.1109/JSSC.2007.891655
[7]
Park J H, Aoyama S, Watanabe T, et al. A high-speed low-noise CMOS image sensor with 13-b column-parallel single-ended cyclic ADCs. IEEE Trans Electron Devices, 2009, 56(11):2414 doi: 10.1109/TED.2009.2030635
[8]
Razavi B. Design of analog CMOS integrated circuits. New York: McGraw-Hill, 2001
[9]
Hwang K. Computer arithmetic principles, architecture and design. New York: John Wiley & Sons, 1979
[10]
Andrew A, Paul G. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits, 1999, 34(5):599 doi: 10.1109/4.760369
[11]
Bigas M, Cabrujaa E, Forest J, et al. Review of CMOS image sensors. Solid-State Electron, 2006, 37:433
[12]
Theuwissen J, Albert P. CMOS image sensors:state-of-the-art. Solid-State Electron, 2008, 52:1401 doi: 10.1016/j.sse.2008.04.012
[13]
Zhang Na. Research on key techniques of super high speed digital CMOS image sensor. Dissertation for the Doctoral Degree, Tianjin: Tianjin University, 2008(in Chinese)
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    Received: 21 January 2013 Revised: 16 February 2013 Online: Published: 01 August 2013

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      Ye Han, Quanliang Li, Cong Shi, Nanjian Wu. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors[J]. Journal of Semiconductors, 2013, 34(8): 085016. doi: 10.1088/1674-4926/34/8/085016 ****Y Han, Q L Li, C Shi, N J Wu. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors[J]. J. Semicond., 2013, 34(8): 085016. doi: 10.1088/1674-4926/34/8/085016.
      Citation:
      Ye Han, Quanliang Li, Cong Shi, Nanjian Wu. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors[J]. Journal of Semiconductors, 2013, 34(8): 085016. doi: 10.1088/1674-4926/34/8/085016 ****
      Y Han, Q L Li, C Shi, N J Wu. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors[J]. J. Semicond., 2013, 34(8): 085016. doi: 10.1088/1674-4926/34/8/085016.

      A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

      DOI: 10.1088/1674-4926/34/8/085016
      Funds:

      the National Natural Science Foundation of China 61234003

      the Special Funds for Major State Basic Research Project of China 2011CB932902

      Project supported by the National Natural Science Foundation of China (Nos. 60976023, 61234003) and the Special Funds for Major State Basic Research Project of China (No. 2011CB932902)

      the National Natural Science Foundation of China 60976023

      More Information
      • Corresponding author: Wu Nanjian, Email:nanjian@semi.ac.cn
      • Received Date: 2013-01-21
      • Revised Date: 2013-02-16
      • Published Date: 2013-08-01

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