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Sen Li, Jinguang Jiang, Xifeng Zhou, Jianghua Liu. A low phase noise and low spur PLL frequency synthesizer for GNSS receivers[J]. Journal of Semiconductors, 2014, 35(1): 015004. doi: 10.1088/1674-4926/35/1/015004
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S Li, J G Jiang, X F Zhou, J H Liu. A low phase noise and low spur PLL frequency synthesizer for GNSS receivers[J]. J. Semicond., 2014, 35(1): 015004. doi: 10.1088/1674-4926/35/1/015004.
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A low phase noise and low spur PLL frequency synthesizer for GNSS receivers
DOI: 10.1088/1674-4926/35/1/015004
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Abstract
A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector (PFD) produces four control signals, which can reach the charge pump (CP) simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.-
Keywords:
- PLL frequency synthesizer,
- phase noise,
- spur,
- PFD,
- CP,
- VCO
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References
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