Fig. 1.
Two-plane interconnect structure.
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| Citation: |
Xiaoxian Liu, Zhangming Zhu, Yintang Yang, Fengjuan Wang, Ruixue Ding. Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips[J]. Journal of Semiconductors, 2014, 35(1): 015008. doi: 10.1088/1674-4926/35/1/015008
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X X Liu, Z M Zhu, Y T Yang, F J Wang, R X Ding. Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips[J]. J. Semicond., 2014, 35(1): 015008. doi: 10.1088/1674-4926/35/1/015008.
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Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips
DOI: 10.1088/1674-4926/35/1/015008
More Information
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Abstract
In high speed three-dimensional integrated circuits (3D ICs), through silicon via (TSV) insertion causes impedance discontinuities along the interconnect-TSV channel that results in signal reflection. As demonstrated for a two-plane interconnect structure connected by a TSV, we incorporate an appropriate capacitance at the junction to mitigate the signal reflection with gigascale frequencies. Based on 65 nm technology and S-parameter analysis, the decrease of signal reflection can be 189% at the tuned frequency of 5 GHz. Extending this method to the five-plane interconnect structure further, the reduction of signal reflection can achieve 400%. So we could broaden this method to any multilevel 3D interconnect structures. This method can also be applied to a circuit with tunable operating frequencies by digitally connecting the corresponding matching capacitance into the circuit through switches. There are remarkable improvements of the quality of the transmitting signals.-
Keywords:
- 3D integration,
- TSV,
- signal reflection,
- impedance matching,
- S-parameter
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References
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