Fig. 1.
The proposed MDAC architecture.
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| Citation: |
Shubin Liu, Zhangming Zhu, Yintang Yang, Lianxi Liu. A programmable MDAC with power scalability[J]. Journal of Semiconductors, 2014, 35(1): 015011. doi: 10.1088/1674-4926/35/1/015011
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S B Liu, Z M Zhu, Y T Yang, L X Liu. A programmable MDAC with power scalability[J]. J. Semicond., 2014, 35(1): 015011. doi: 10.1088/1674-4926/35/1/015011.
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Abstract
A programmable high precision multiplying DAC (MDAC) is proposed. The MDAC incorporates a frequency-current converter (FCC) to adjust the power versus sampling rate and a programmable operational amplifier (POTA) to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW (10 MHz) to 63 mW (100 MHz) while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively. -
References
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