Fig. 1.
(a) Gate level implementation of the proposed PFD. (b) Diagram of blind zone production.
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| Citation: |
Faen Liu, Zhigong Wang, Zhiqun Li, Qin Li, Sheng Chen. Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop[J]. Journal of Semiconductors, 2014, 35(10): 105006. doi: 10.1088/1674-4926/35/10/105006
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F E Liu, Z G Wang, Z Q Li, Q Li, S Chen. Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop[J]. J. Semicond., 2014, 35(10): 105006. doi: 10.1088/1674-4926/35/10/105006.
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Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop
DOI: 10.1088/1674-4926/35/10/105006
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Abstract
Two essential blocks for the PLLs based on CP, a phase-frequency detector (PFD) and an improved current steering charge-pump (CP), are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354 ° to 354 ° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply. -
References
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