1. Introduction

The phase-frequency detector (PFD) and charge-pump (CP) are widely used in modern phase-locked loops (PLLs), which are the key building blocks for clock generation and recovery in modern communication systems^{[1, 2]}. The PFD is a circuit that can detect both phase and frequency difference between two input signals and generate outputs representing the corresponding difference. The CP, connected to the outputs of the PFD, is used to pump-in or pump-out current from the loop-filter. In practice, nonidealities of PFD and CP degrade the performance of the loop. For PFD, the presence of the dead zone makes the loop fail to correct the error when the phase difference reaches a certain small value. As a result, the loop is essentially open and the phase noise of the loop is increased. Meanwhile, a narrow phase error detection range may lead to detection error and increase the loop locking time. For CP, the mismatch between the charging and discharging current increases the level of the reference spurs and produces steady-state phase offset. Glitches existing in the output current also increase the spurs and variation of the output current will vary the loop bandwidth.

In recent years, researches on PFD have been carried out to simplify the circuit, eliminate the dead zone and reduce the blind zone^{[3, 4]}, and techniques on CP have been utilized to realize a wide output voltage range with excellent current matching and minimum current variation^{[5, 6]}. Various PFD architectures for PLLs are analyzed and compared in Ref. [3]. Simulations are carried out to show the performance of the different PFDs. In Ref. [4], analysis of the blind zone production for the TSPC based PFD is presented and two transistors are adopted to alleviate the blind zone caused by the precharge time of the internal nodes. A full-swing CP with zero phase offset is proposed in Ref. [5]. With the help of the additional amplifier and NMOS-PMOS transistor pair, the problems of current mismatch, charging sharing and channel charge injection are solved. However, the simulated result shows that the variation for the pump current is within 5.4%, which is not very good. For minimum current variation, a new CP with adaptive body-bias compensation is present in Ref. [6], which is only verified by simulations and may suffer the problem that the CP has to be isolated from the switching noise in a separate well.

In this paper, optimizing the conventional PFD with a minimum blind zone and a novel CP with accurate current match and minimum current variation across a wide output voltage range are designed and implemented in a standard 90-nm CMOS process. The measured results show that a wide phase error detection range from -354° to 354° is achieved for the proposed PFD, and the CP produces a wide output voltage from 0.2 to 1.1 V where the current mismatch and variation are less than 1.1% and 4%, respectively.

2. Optimizing PFD with zero dead zone and a wide phase error detection range

For a 50-MHz operation frequency, a conventional PFD is developed in this design. The gate level implementation of the proposed PFD is shown in Fig. 1(a), which consists of two edge-triggered resettable D flip-flops and a four-input NAND. To eliminate the dead zone, a delay cell in the reset path is implemented by employing two inverters, which ensures the output pulses are sufficient to turn-ON (or turn-OFF) the switch transistors of the CP. Due to the existence of the edge-triggered delay and the reset delay, a blind zone is produced which makes the phase error detection range lower than 2π^[4].

The diagram of the blind zone production is shown in Fig. 1(b). Assuming the minimum pulse duration of the output signal for zero-dead zone is T_min, the duration of the blind zone can be expressed as

$T_{\rm BZ} =T_{\rm DFF} +T_{\rm min} +T_{\rm d} =T_{\rm DFF} +T_{\rm rst} +2T_{\rm d},$

(1)

where T_DFF is the response time of the edge-triggered D flip-flops, T_d is the delay time of the two-input NAND and the inverters, and T_rst is the pulse duration of the reset signal. As shown in Fig. 1(b), if the rising edge of the REF signal falls at the blind zone, it would not be detected and lead to phase detection error.

The maximum phase error detection range can be derived as

$\Delta {\theta _{{\rm{max}}}} = 4\pi \left( {1 - \frac{{{T_{{\rm{BZ}}}}}}{{{T_{\rm{P}}}}}} \right) = 4\pi \left( {1 - \frac{{{T_{{\rm{DFF}}}} + {T_{{\rm{rst}}}} + 2{T_{\rm{d}}}}}{{{T_{\rm{P}}}}}} \right),$

(2)

where T_P is the period of the input signal. As T_min is usually a constant value for zero-dead zone, the maximum phase error detection range can be enlarged by decreasing the response time T_DFF of the edge-triggered D flip-flops.

3. Improved CP with reduced circuit mismatch, variation and transient glitches

An improved current steering charge pump with superior performance is proposed and the architecture is shown in Fig. 2. Two rail-to-rail amplifies, AMP1 and AMP2, are employed for accurate current matching and reduced charge sharing, respectively. To decrease the current variation and transient glitches, the current compensation circuit and clock feed through the reduction circuit are fully utilized. Furthermore, an accelerating acquisition circuit is adopted in the proposed CP to help the PLL accelerate acquisition and reduce the acquisition time.

3.1 Rail-to-rail amplifiers for accurate current matching and reduced charge injection produced by charge sharing

The charging and discharging current curves for a conventional CP is shown in Fig. 3(a). Due to the channel-length modulation effect, the charging current is larger than the discharging current when the output voltage is lower than half of the supply voltage, while on the other hand, the charging current is lower than the discharging current when the output voltage is larger than half of the supply voltage. For the PLL to remain locked, a phase error between f_DIV and f_REF is created, such that the net current produced by the CP in every cycle is zero and the average value of the control voltage is constant. However, cyclical variation is produced for the control voltage, which generates output spurs for the PLL.

As described in the reported paper^[5], a rail-to-rail error amplifier AMP1 with a high gain is utilized to make the voltage V_ref of the current mirror follow the output voltage V_out accurately. As a result, the charging current I_up is equal to the discharging current I_DN and the simulated result is shown in Fig. 3(b). Owing to the utilization of the AMP1, two feedback loops, a negative feedback loop and a positive feedback loop, are introduced which will affect the stability of the circuit. In our design, resistor R₁ and capacitor C₁ are employed to improve the phase margin and guarantee the stability. Figure 4 shows the simulated phase margin of the feedback loops. It fluctuates between 60.5° and 85.4° when the output voltage V_out ranges from 0.1 to 1.1 V. Another rail-to-rail amplifier AMP2 is employed to reduce the charge injection produced by the charge sharing between V_A and V_B. As shown in Fig. 2, two routes are utilized in the proposed CP and there is always one route available when the other one is shut off. The charge sharing will be eliminated as the voltages V_A and V_B keep constant for the locked PLL and the periodical charge flowing into or out from the loop filter is removed.

3.2 Current compensation circuit for current variation reduction

As shown in Fig. 3(b), when the output voltage V_out descends gradually, the charging and discharging current decreases rapidly due to the channel modulation of the mirror transistors. The variation of the output current results in changes of the loop bandwidth, which causes the PLL instability.

To solve this problem, a dynamic current compensation circuit, shown in Fig. 5(a), is utilized in the proposed CP^[7]. When the output voltage V_out decreases towards zero, the gate-to-source voltage of M16 is enlarged gradually and an enhanced current is produced to compensate the reduction of the pump current. On the other hand, when V_out goes high, transistor M16 is "off" and the compensation current is removed accordingly. The modified current matching curves are shown in Fig. 5(b). The current variation is weakened significantly and controlled within 2% for an extended range from 0.1 to 1.1 V.

3.3 Clock feed through the reduction circuit for transient glitches suppression

When the input voltages switch from V_L to V_H or V_H to V_L, high-speed glitches are produced by charging or discharging the gate-to-drain capacitance of the switch transistors, which inject current into the output node. To reduce the injection current produced by the clock feed glitches, another two transistors M5 and M6 are employed and the schematic is shown in Fig. 6. The source terminals of M5 and M6 are left floating to avoid extra DC current. With the same transistor sizes and equal equivalent parasitic capacitance, the glitches on the pump current induced by the switching of DN and UP are canceled by the ones induced by DNB and UPB.

3.4 Accelerating acquisition circuit

As shown in Fig. 5(b), a small charging current is achieved for a low output voltage V_out. When V_out changes from 0 to 1.2 V, the acquisition time for the PLL is long due to the small charging current. In our proposed design, a modified accelerating acquisition circuit consisting of two PMOS transistors with a constant bias voltage V_BN is employed, and its schematic is shown in Fig. 7. For the CP with the accelerating acquisition circuit shown in Fig. 2, when V_out is high, amplifier AMP1 has a high gain and the pump current is copied accurately due to V_ref following V_out perfectly. When V_out is reduced to zero, amplifier AMP1 cannot make V_ref follow V_out and an additional current is produced through transistors M9 and M10, which makes the current I_up keep a large value while I_DN becomes small rapidly due to transistors M2 and M8 being at the linear area. The simulated curves of the charging and discharging current are shown in Fig. 13. The charging current keeps a large level for a small V_out, which helps the PLL to accelerate acquisition and reduce the locking time. Figure 8 shows the current mismatching curves of the proposed CP under FS and SF corner-cases and a different temperature. Although the current mismatch has a tiny enlargement as the temperature is increased, excellent current matches are also achieved.

4. Circuit design

The connection diagram of the PFD and CP is shown in Fig. 9. The PFD is responsible to detect both the phase and frequency difference between input signals and generates outputs which represent the difference, and its schematic is shown in Fig. 1(a). Two inverters are employed as the delay cell in the reset path to ensure the output pulses are sufficient to turn-ON (OFF) the switch transistors of the CP. Confirmed through simulation, the dead zone is eliminated. Customized NAND gates are utilized in this design to form the D flip-flops. By properly choosing the sizes of the NMOS and PMOS transistors in the NAND gates, the response time T_DFF of the edge-triggered D flip-flops is decreased, such that the maximum phase error detection range is enlarged. The optimum widths of the NMOS and PMOS transistors in the NAND gates are 1 × 6.4 μm and 1 × 8 μm, respectively. For 50-MHz input signals, an enlarged detection range from -356° to 356° is achieved. The phase error detection range curve is shown in Fig. 12.

The CP, connected to the outputs of the PFD, is utilized to pump-in or pump-out the current from the loop-filter and produce a smooth control voltage for the voltage-controlled oscillator (VCO). The schematic of the proposed CP is shown in Fig. 2, which consists of switches M1-M6, current source transistors M7-M9 providing a constant reference current and current mirrors M10-M13. The transistors M14 and M15, with the same sizes of M1 and M2, are employed to match the voltage drop across the switches, and the reference current can be accurately mirrored to M1 and M2. The transistors M16 and M17 are utilized to produce a dynamic compensation current, which helps to eliminate the current variation. To increase the switching speed and minimize the glitches, the switch transistors are always kept in the saturation region for a small gate-to drain capacitance, and the optimum size of the transistors is 1.8 × 15 μm in this particular design. Meanwhile, the cross match structure is utilized in the layout design of the switch transistors to avoid mismatch.

5. Measured performance and conclusions of the proposed PFD and CP

The proposed PFD and CP are implemented using a standard 90-nm CMOS process. The chip microphotograph is shown in Fig. 10. It occupies an area of 0.56 × 0.54 mm². The power consumption of the circuit is 1.3 mW at a 1.2 V supply voltage.

On-wafer measurements have been performed by using a Tektronix AFG3252 2 Gs/s 240 MHz and an Agilent technologies IVISO9254A mixed signal oscilloscope 2.5 GHz 20 GS/s. Two 50-MHz square signals are produced by the signal generator and sent to the input of the PFD. As shown in Fig. 11, the measured reset pulse duration is 200 ps, which is larger than the simulated one (150 ps). The measured phase error detection curve is shown in Fig. 12 and a detection range from -354° to 354° is achieved, which agrees well with the analytical results.

The measured charging and discharging current match curves of the proposed CP are shown in Fig. 13. When the output voltage V_out varies from 0.2 to 1.1 V, the output current mismatch ratio is less than 1.1%. Meanwhile, the pump currents fluctuate between 90 and 93.7 μA across the matching range, and the current variation is controlled within 4%. When the output voltage decreases to zero, the charging current is still larger than 80 μA, which can reduce the acquisition time of PLLs. Table 1 summarizes the performance of the proposed CP and makes comparisons with other reported CPs in terms of the current mismatch ratio, voltage swing and current variation. It is superior to others in both the current mismatch ratio and current variation.

Figure 14 shows the charging and discharging process of the proposed PFD and CP. A 1-pF capacitor is connected to the output of the CP. When the phase of F_REF is advanced, charging current I_UP is produced and the output voltage increases from 0.033 to 1.01 V, shown in Fig. 14(a). On the other hand, when the phase of FDIV is advanced, discharging current IDN is produced and the output voltage decreases from 1 to 0.032 V, shown in Fig. 14(b). Notably, the total circuit has the right function for the charging and discharging process.

6. Conclusion

An optimal PFD with zero-dead zone is developed due to the utilization of the delay unit. To extend the phase error detection range, the response time of the edge-triggered D flip-flops is reduced by properly choosing the sizes of the NMOS and PMOS transistors in the NAND gates. An improved CP consisting of two rail-to-rail amplifiers, a current compensation circuit, the clock feed through the reduction circuit and an accelerating acquisition circuit is demonstrated and superior performance in high speed applications is obtained. The proposed circuits are fabricated using a standard 90-nm CMOS process and the overall chip area is 0.56 × 0.54 mm². The test results of the PFD and CP indicate that they are suitable to provide a smooth control voltage for the VCO in frequency synthesizer applications.

Acknowledgments: The authors would like to thank Li Wei and Zhang Li of the Institute of RF-&OE-ICs for their generous support.