Fig. 1.
Structure for FELERION.
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| Citation: |
R Anjana, Ajay Somkuwar. FELERION:a new approach for leakage power reduction[J]. Journal of Semiconductors, 2014, 35(12): 125001. doi: 10.1088/1674-4926/35/12/125001
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R Anjana, A Somkuwar. FELERION:a new approach for leakage power reduction[J]. J. Semicond., 2014, 35(12): 125001. doi: 10.1088/1674-4926/35/12/125001.
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FELERION:a new approach for leakage power reduction
DOI: 10.1088/1674-4926/35/12/125001
More Information
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Abstract
The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%-94% as compared to the conventional approach.-
Keywords:
- leakage power,
- sleep transistors,
- FELERION,
- scaling,
- propagation delay,
- power dissipation
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References
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