J. Semicond. > 2014, Volume 35 > Issue 3 > 034012
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SEMICONDUCTOR DEVICES

High efficiency modeling of broadband millimeter-wave CMOS FETs with gate width scalability by using pre-modeled cells

Yang Tang, Zuochang Ye and Yan Wang

+ Author Affiliations

 Corresponding author: Wang Yan, Email: wangy46@tsinghua.edu.cn

DOI: 10.1088/1674-4926/35/3/034012

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Abstract: This work presents a highly efficient approach for broadband modeling of millimeter-wave CMOS FETs with gate width scalability by using pre-modeled cells. Only a few devices with varied gate width are required to be measured and modeled with fixed models, and later used as pre-modeled cells. Then a target device with the desired gate width is constructed by choosing appropriate cells and connecting them with a wiring network. The corresponding scalable model is constructed by incorporating the fixed models of the cells used in the target device and the scalable model of the connection wires. The proposed approach is validated by experiments on 65-nm CMOS process up to 40 GHz and across a wide range of gate widths.

Key words: CMOS MOSFETs, layout, millimeter-wave, scalable model



[1]
Long J R, Zhao Y, Wu W H, et al. Passive circuit technologies for mm-wave wireless systems on silicon. IEEE Trans Circuits Syst Ⅰ:Regular Papers, 2012, 59(8):1680 doi: 10.1109/TCSI.2012.2206499
[2]
Doan C H, Emami S, Niknejad A M, et al. Millimeter-wave CMOS design. IEEE J Solid-State Circuits, 2005, 40(1):144 doi: 10.1109/JSSC.2004.837251
[3]
Heydari B, Bohsali M, Adabi E, et al. Millimeter-wave devices and circuit blocks up to 104 GHz in 90 nm CMOS. IEEE J Solid-State Circuits, 2007, 42(12):2893 doi: 10.1109/JSSC.2007.908743
[4]
Suzuki T, Kawano Y, Sato M, et al. 60 and 77 GHz power amplifiers in standard 90 nm CMOS. IEEE International Solid-State Circuits Conference, 2008:562 http://gradworks.proquest.com/33/53/3353454.html
[5]
Dabag H T, Hanafi B, Golcuk F, et al. Analysis and design of stacked-FET millimeter-wave power amplifiers. IEEE Trans Microw Theory Tech, 2013, 61(4):1543 doi: 10.1109/TMTT.2013.2247698
[6]
Kim H S, Kim J, Chung C, et al. Effects of parasitic capacitance, external resistance, and local stress on the RF performance of the transistors fabricated by standard 65-nm CMOS technologies. IEEE Trans Electron Device, 2008, 55(10):2712 doi: 10.1109/TED.2008.2003995
[7]
Kim H S, Park K, Oh H, et al. Effective gate layout methods for RF performance enhancement in MOSFETs. IEEE Electron Device Lett, 2009, 30(10):1105 doi: 10.1109/LED.2009.2029128
[8]
Chan C Y, Chen S C, Tsai M H, et al. Wiring effect optimization in 65-nm low-power NMOS. IEEE Electron Device Lett, 2008, 29(11):1245 doi: 10.1109/LED.2008.2005515
[9]
Kang I M, Jung S J, Choi T H, et al. Scalable model of substrate resistance components in RF MOSFETs with bar-type body contact considered layout dimensions. IEEE Electron Device Lett, 2009, 30(4):404 doi: 10.1109/LED.2009.2014085
[10]
Choi W, Jung G, Kim J, et al. Scalable small-signal modeling of RF CMOS FET based on 3-D EM-based extraction of parasitic effects and its application to millimeter-wave amplifier design. IEEE Trans Microw Theory Tech, 2009, 57(12):3345 doi: 10.1109/TMTT.2009.2034067
[11]
Gao J, Werthof A. Direct parameter extraction method for deep sub-micrometer metal oxide semiconductor field effect transistor small signal equivalent circuit. IET Microwaves, Antennas & Propagation, 2009, 3(4):564 http://cpb.iphy.ac.cn/EN/Y2005/V14/I4/808
[12]
Chi Y S, Lu J X, Zhang S Y, et al. An analytical parameter extraction of the small-signal model for RF MOSFETs. IEEE Conference on Electron Devices and Solid-State Circuits, 2005:555 http://ieeexplore.ieee.org/document/1635332/
[13]
Chi Yusong, Huang Fengyi, Wu Zhongjie, et al. Characterization and modeling for 0.13μm RF MOSFETs. Chinese Journal of Semiconductors, 2006, 27(2):373 http://www.oalib.com/paper/1522269
[14]
Liu Jun, Sun Lingling, Xu Xiaojun. RF-CMOS modeling:RF-MOSFET modeling for low power applications. Chinese Journal of Semiconductors, 2007, 28(1):131 http://www.oalib.com/paper/1522446
[15]
Kwon I, Je M, Lee K, et al. A simple and analytical parameter-extraction method of a microwave MOSFET. IEEE Trans Microw Theory Tech, 2002, 50(6):1503 doi: 10.1109/TMTT.2002.1006411
[16]
Cho S, Kim K R, Park B G, et al. RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs. IEEE Trans Electron Device, 2011, 58(5):1388 doi: 10.1109/TED.2011.2109724
[17]
Tang Y, Zhang L, Wang Y. Accurate small signal modeling and extraction of silicon MOSFET for RFIC application. Solid-State Electron, 2010, 54(11):1312 doi: 10.1016/j.sse.2010.06.025
Fig. 1.  Illustration of the layout approach using pre-modeled cells and the conventional layout approach. (a) A 116 $\mu $m device is achieved by using cells with gate width 64, 32, 16 and 4 $\mu $m which are connected by gate, drain and source wires outside the cell boundaries. Cell boundaries are indicated by dashed rectangles. All the layouts, performance, and parasitic effects inside the cell boundaries stay unchanged. (b) Conventional method directly scales a single device up to 116 $\mu $m.

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Fig. 2.  (a) Schematic illustration of detailed layout for the parasitic capacitance and resistance modeling. The currents, parasitic resistance and capacitance in connection wires are overlaid in the layout. (b) The scalable model constructed according to the layout in (a) by combining parasitic model of wires and fixed model of each cell. Only the model of cell nf1 is shown, other cells use the same model with different model parameters. (c) The small-signal equivalent model of cells used in (b) is plotted in detail.

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Fig. 3.  The measured (markers) and model simulated (solid line) frequency dependence of (a) $g_{\rm m}^{\rm t}$, (b) $C_{\rm gd}^{\rm t}$, (c) $C_{\rm g}^{\rm t}$ and (d) $C_{\rm d}^{\rm t}$ of the validation devices (gate width 15, 75, 150 and 240 $\mu $m, at $V_{\rm g}$ $=$ 1.2 V, $V_{\rm d}$ $=$ 1.2 V). The curves are normalized to gate width. Difference between measurement and simulation is exaggerated by deliberately setting $Y$ axis to a small range but the error is in fact rather small. $g_{\rm m}^{\rm t}$, $C_{\rm gd}^{\rm t}$, $C_{\rm g}^{\rm t}$ and $C_{\rm d}^{\rm t}$ are very sensitive to the accuracy of parasitic resistance and capacitance of terminal wires. Close agreement between measurement and simulation demonstrated the feasibility and accuracy of the proposed approach.

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Fig. 4.  (a) $S$-parameters and (b) $H_{21}$ current gain comparison of the proposed model, conventional model and measured data for a validation device (150 $\mu $m gate width, at $V_{\rm g}$ $=$ 1.2 V, $V_{\rm d}$ $=$ 1.2 V, 0.1-40 GHz). (a) The proposed model agrees with data much better than conventional model at the low frequency end of the $S_{21}$ and $S_{22}$ curves and at the high frequency end of the $S_{12}$ curves. (b) The cutoff frequency $f_{\rm t}$ extracted from the $H_{21}$ are 156 GHz, 147 GHz and 133 GHz respectively. The proposed model predicts the important figures of merit (FOMs) more accurately.

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Fig. 5.  Device performance ($S$-parameters) dependence on gate width is plotted using the proposed model (gate width sweeping from 4 to 250 $\mu $m with 4 $\mu $m step, at 24 GHz, $V_{\rm g}$ $=$ 1.2 V, $V_{\rm d}$ $=$ 1.2 V). The $S_{21}$ of cell devices (gate width 1, 2, 4, 8, 16, 32, 64, 128 $\mu $m) and validation devices (gate width 15, 75, 150, 240 $\mu $m) at 24 GHz are also added and highlighted as reference. The simulated $S$-parameters move clockwise with increase of gate width which clearly shows the dependence of device performance on gate width.

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Table 1.   Transconductance and capacitances of the measured and the scalable model predicted devices at 24 GHz with Vg = 1.2 V, Vd = 1.2 V.
[1]
Long J R, Zhao Y, Wu W H, et al. Passive circuit technologies for mm-wave wireless systems on silicon. IEEE Trans Circuits Syst Ⅰ:Regular Papers, 2012, 59(8):1680 doi: 10.1109/TCSI.2012.2206499
[2]
Doan C H, Emami S, Niknejad A M, et al. Millimeter-wave CMOS design. IEEE J Solid-State Circuits, 2005, 40(1):144 doi: 10.1109/JSSC.2004.837251
[3]
Heydari B, Bohsali M, Adabi E, et al. Millimeter-wave devices and circuit blocks up to 104 GHz in 90 nm CMOS. IEEE J Solid-State Circuits, 2007, 42(12):2893 doi: 10.1109/JSSC.2007.908743
[4]
Suzuki T, Kawano Y, Sato M, et al. 60 and 77 GHz power amplifiers in standard 90 nm CMOS. IEEE International Solid-State Circuits Conference, 2008:562 http://gradworks.proquest.com/33/53/3353454.html
[5]
Dabag H T, Hanafi B, Golcuk F, et al. Analysis and design of stacked-FET millimeter-wave power amplifiers. IEEE Trans Microw Theory Tech, 2013, 61(4):1543 doi: 10.1109/TMTT.2013.2247698
[6]
Kim H S, Kim J, Chung C, et al. Effects of parasitic capacitance, external resistance, and local stress on the RF performance of the transistors fabricated by standard 65-nm CMOS technologies. IEEE Trans Electron Device, 2008, 55(10):2712 doi: 10.1109/TED.2008.2003995
[7]
Kim H S, Park K, Oh H, et al. Effective gate layout methods for RF performance enhancement in MOSFETs. IEEE Electron Device Lett, 2009, 30(10):1105 doi: 10.1109/LED.2009.2029128
[8]
Chan C Y, Chen S C, Tsai M H, et al. Wiring effect optimization in 65-nm low-power NMOS. IEEE Electron Device Lett, 2008, 29(11):1245 doi: 10.1109/LED.2008.2005515
[9]
Kang I M, Jung S J, Choi T H, et al. Scalable model of substrate resistance components in RF MOSFETs with bar-type body contact considered layout dimensions. IEEE Electron Device Lett, 2009, 30(4):404 doi: 10.1109/LED.2009.2014085
[10]
Choi W, Jung G, Kim J, et al. Scalable small-signal modeling of RF CMOS FET based on 3-D EM-based extraction of parasitic effects and its application to millimeter-wave amplifier design. IEEE Trans Microw Theory Tech, 2009, 57(12):3345 doi: 10.1109/TMTT.2009.2034067
[11]
Gao J, Werthof A. Direct parameter extraction method for deep sub-micrometer metal oxide semiconductor field effect transistor small signal equivalent circuit. IET Microwaves, Antennas & Propagation, 2009, 3(4):564 http://cpb.iphy.ac.cn/EN/Y2005/V14/I4/808
[12]
Chi Y S, Lu J X, Zhang S Y, et al. An analytical parameter extraction of the small-signal model for RF MOSFETs. IEEE Conference on Electron Devices and Solid-State Circuits, 2005:555 http://ieeexplore.ieee.org/document/1635332/
[13]
Chi Yusong, Huang Fengyi, Wu Zhongjie, et al. Characterization and modeling for 0.13μm RF MOSFETs. Chinese Journal of Semiconductors, 2006, 27(2):373 http://www.oalib.com/paper/1522269
[14]
Liu Jun, Sun Lingling, Xu Xiaojun. RF-CMOS modeling:RF-MOSFET modeling for low power applications. Chinese Journal of Semiconductors, 2007, 28(1):131 http://www.oalib.com/paper/1522446
[15]
Kwon I, Je M, Lee K, et al. A simple and analytical parameter-extraction method of a microwave MOSFET. IEEE Trans Microw Theory Tech, 2002, 50(6):1503 doi: 10.1109/TMTT.2002.1006411
[16]
Cho S, Kim K R, Park B G, et al. RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs. IEEE Trans Electron Device, 2011, 58(5):1388 doi: 10.1109/TED.2011.2109724
[17]
Tang Y, Zhang L, Wang Y. Accurate small signal modeling and extraction of silicon MOSFET for RFIC application. Solid-State Electron, 2010, 54(11):1312 doi: 10.1016/j.sse.2010.06.025

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    Received: 16 August 2013 Revised: 07 October 2013 Online: Published: 01 March 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(3): 034012
      Yang Tang, Zuochang Ye, Yan Wang. High efficiency modeling of broadband millimeter-wave CMOS FETs with gate width scalability by using pre-modeled cells[J]. Journal of Semiconductors, 2014, 35(3): 034012. doi: 10.1088/1674-4926/35/3/034012 ****Y Tang, Z C Ye, Y Wang. High efficiency modeling of broadband millimeter-wave CMOS FETs with gate width scalability by using pre-modeled cells[J]. J. Semicond., 2014, 35(3): 034012. doi: 10.1088/1674-4926/35/3/034012.
      Citation:
      Yang Tang, Zuochang Ye, Yan Wang. High efficiency modeling of broadband millimeter-wave CMOS FETs with gate width scalability by using pre-modeled cells[J]. Journal of Semiconductors, 2014, 35(3): 034012. doi: 10.1088/1674-4926/35/3/034012 ****
      Y Tang, Z C Ye, Y Wang. High efficiency modeling of broadband millimeter-wave CMOS FETs with gate width scalability by using pre-modeled cells[J]. J. Semicond., 2014, 35(3): 034012. doi: 10.1088/1674-4926/35/3/034012.
      shu

      High efficiency modeling of broadband millimeter-wave CMOS FETs with gate width scalability by using pre-modeled cells

      DOI: 10.1088/1674-4926/35/3/034012

      • Institute of Microelectronics, Tsinghua University, Beijing 100084, China

      Funds:

      the Major State Basic Research Development Program of China 2010CB327403

      Project supported by the Major State Basic Research Development Program of China (No. 2010CB327403)

      More Information
      • Corresponding author: Wang Yan, Email: wangy46@tsinghua.edu.cn
      • Received Date: 2013-08-16
      • Revised Date: 2013-10-07
      • Published Date: 2014-03-01

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