Fig. 1.
The comparator block diagram
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| Citation: |
Kai Tang, Qiao Meng, Zhigong Wang, Ting Guo. A low power 20 GHz comparator in 90 nm COMS technology[J]. Journal of Semiconductors, 2014, 35(5): 055002. doi: 10.1088/1674-4926/35/5/055002
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K Tang, Q Meng, Z G Wang, T Guo. A low power 20 GHz comparator in 90 nm COMS technology[J]. J. Semicond., 2014, 35(5): 055002. doi: 10.1088/1674-4926/35/5/055002.
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A low power 20 GHz comparator in 90 nm COMS technology
DOI: 10.1088/1674-4926/35/5/055002
More Information
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Abstract
A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65×150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.-
Keywords:
- comparator,
- ADC,
- ultra-high-speed,
- low power,
- latch,
- CMOS
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References
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