1. Introduction

The delay-locked loop (DLL) is an essential building block of some important components in field programmable gate array (FPGA) chips such as clock generation^[1], clock multiplication^[2] and high-speed clock/data recovery (CDR)^[3]. Static phase error performance and the number of output phases are two important issues in DLL design. However, it is a tradeoff between the number of output phases and static phase error performance with a constant phase resolution. The static phase error performance will deteriorate when the number of output phases increases. For a DLL used in FPGA chips, it faces various application requirements of different output phases and static phase error performance. The conventional DLLs have fixed four or more output phases^[2-5]. They cannot satisfy the applications in which fewer output phases but a higher static phase error performance are needed.

To cover the wide application requirements, it is straightforward to adopt several DLLs with different static phase error performances and output phases in a single FPGA chip. However, this will cause large power consumption and high area cost. Thus, it is necessary to combine the trait of small static phase error and multiphase output in one DLL circuit. This paper proposes a multimode DLL with different output phases and static phase error performance. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL has three operation modes: mode1 with four-phase output, mode2 with two-phase output and better static phase error performance, and mode3 with only one-phase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 $\mu$m CMOS technology and measurement results show that the static phase errors of mode1, mode2 and mode3 are -18.2 ps, 11.8 ps and $-6.44$ ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively.

2. General idea of proposed multimode delay line

Generally, a DLL provides multiphase outputs by connecting multiple identical delay cells serially into a delay line (DL). Figure 1(a) shows a conventional DL^[6], which is composed of four identical delay cells. Figure 1(b) shows its timing diagram. The static phase error of each delay cell is equal to its time resolution. In Fig. 1(a), all the delay cells are controlled by the same codes C[n: 0]. Thus, the DLL can output four exactly orthogonal signals (CLK90, CLK180, CLK270 and CLK360). However, these delay cells have the same static phase errors (the same magnitude and the same delay-tune orientation). The total static phase error of the DLL is the accumulation of multiple identical delay cells' static phase errors. Assume that the static phase error of each delay cell is $\Delta t$, the total static phase error of a DLL with this DL is given as:

$\begin{equation} \Delta T=N\cdot \Delta t, \end{equation}$

(1)

where $\Delta T$ is the total static phase error of the DLL, and $N$ represents the number of the delay cells in the DL, which is also equal to the number of output phases. In most cases, $N$ is set to 4. From Eq. (1), it is a tradeoff between the number of output phases and the static phase error performance. The static phase error performance will deteriorate with increasing the number of output phases when $\Delta t$ is a constant value.

Practically, when the resolution of the phase detector (PD) is higher than the one of the DL, regrouping the DL can achieve a better static phase error performance. Figure 2 shows the architecture and timing diagram of the DL in the proposed multimode DLL. There are three modes: mode1 with a four-phase output clock, mode2 with a two-phase output clock and mode3 with a one-phase output clock. The four delay cells^[8] in the proposed DL are identical, and are controlled by the same control codes Code [10:1] but a different first control code Code [0].

Figure 2(a) shows the DL in mode1 with a four-phase output clock. In this mode, the four delay units are controlled by the same control codes Code[10:1] and the same first control code Code $_{0}$[0], thus the DL can provide four accurate orthogonal output clocks. The four delay cells have the same static phase error, e.g. $\Delta t$. Due to the accumulation of static phase error, the static phase errors of CLK180 and CLK360 are $2\Delta t$ and $4\Delta t$ respectively.

To reduce the static phase error of the CLK180 and CLK360, we can regroup the DL to retune the first control codes, as shown in Fig. 2(b). The DL in mode2 is regrouped into two groups, group1 and group2, which are composed of two delay cells represented as delay cell0 and delay cell1 respectively. Group1 and group2 provide the same delays, thus the DL can provide two accurate differential output clocks. Controlled by different codes, each group can tune delay one step by $\Delta t$. Thus the total static phase error of one group can be retuned within $\Delta t$. Then the static phase errors of CLK180 and CLK360 in mode2 are $\Delta t$ and $2\Delta t$ respectively. The working procedure of mode2 is as follows: after completing the similar operation as in mode1, the DL starts to retune the first control codes Code $_{0}$[0] and Code $_{1}$[0] by one step $\Delta t$ to achieve a smaller static phase error from $2\Delta t$ to $\Delta t$ for each group delay cell. Thus the static phase errors of CLK180 and CLK360 are reduced to $\Delta t$ and $2\Delta t$ respectively.

Similarly, to further reduce the static error of CLK360, the four delay cells, which are renamed to delay cell0, delay cell1, delay cell2 and delay cell3, can be regrouped into one group and controlled by different first control codes, as shown in Fig. 2(c). After completing the similar operation as the DL in mode1, the DL starts to retune the delay by one step $\Delta t$. Thus the total static phase error of the DL can be retuned within $\Delta t$. That means the static phase error of CLK360 is reduced to $\Delta t$.

By adopting different first control codes in the delay cells, the DLL achieves three operation modes: mode1 with a four-phase output, mode2 with a two-phase output and a better static phase error performance, and mode3 with only one-phase output but the best static phase error performance. The proposed DLL can cover much wider application requirements than a conventional circuit through the multimode operation.

2.1 Principle of calibration in mode2

Figure 3 shows the concept of the first control code calibration of four cases in mode2. According to the phase relation between CLK_REF and CLK360 after locking in mode1 and the maximum phase error $2\Delta t$ of the whole DL, there are four cases to calibration in mode2. As shown in Fig. 3(a), the feedback clock CLK360 leads the reference clock CLK_REF but beyond the locking range in mode2. As mentioned above, the DL retunes one step delay by 2 $\Delta t$ in mode2. Thus the DL just retunes the one first control code, e.g. Code $_{0}$[0] in Fig. 2(b), to increase one step delay by 2 $\Delta t$ to make the DL be in the locking range of mode2. As shown in Figs. 3(b) and 3(c), after locking in mode1, the phase difference between CLK360 and CLK_REF is within the locking range of the DL in mode2, thus the two first control codes Code $_{0}$[0] and Code $_{0}$[1] just remain initial value. As shown in Fig. 3(d), the feedback clock CLK360 lags the reference clock CLK_REF but beyond the locking range in mode2. Due to the DL initializing the two first control codes to achieve minimum delay, the DL needs to increase delay to get locking for mode2. Firstly, the DL increases one step delay by $2\Delta t$ to make mode1 lost locking. Secondly, the DL in mode1 retunes the control code Code[10:1] to decrease one step delay by $4\Delta t$. Right now, the DL in mode1 gets relocked and the phase difference between CLK360 and CLK_REF is within the locking range of mode2.

2.2 Principle of calibration in mode3

Figure 4 shows the concept of the first control code calibration of eight cases in mode3. Similar to the DL in mode2, there are eight cases to calibration in mode3 according to the phase relation between CLK360 and CLK_REF and the maximum phase error $\Delta t$ of the whole DL. However, the DL in mode3 tunes one step delay by $\Delta t$ different from the DL in mode2 by $2\Delta t$.

As shown in Fig. 4(a), firstly, the DL needs to tune one first control code, e.g. Code $_{0}$[0] in Fig. 2(c), to increase one step delay by $\Delta t$. Due to the DL not getting locked, the DL needs to tune one another's first control code, e.g. Code $_{0}$[1], to increase one step delay by $\Delta t$ to get locked for mode3. As shown in Figs. 4(b) and 4(c), the DL needs to increase one step delay by $\Delta t$ to get locked. In Figs. 4(d) and 4(e), after locking in mode1, the phase difference between CLK360 and CLK_REF is within the locking range of the DL in mode3, thus the four first control codes Code $_{0}$[0], Code $_{0}$[1], Code $_{0}$[2] and Code $_{0}$[3] just remain at the initial value. As shown in Figs. 4(f), 4(g) and 4(h), their operation principles are similar to the one of the DL in mode2 in Fig. 3(d). Due to the DL initializing the four first control codes to achieve minimum delay, the DL needs to increase delay to get locking for mode3. Firstly, the DL increases delay step by step until the DL in mode1 gets unlocked. Then, the DL in mode1 decreases one step delay by $4\Delta t$ to make the DL relock. Right now, the feedback clock CLK360 changes to from lag to leading the reference clock CLK_REF. Finally, the DL in mode3 increase delay step by step until the DL in mode3 gets locked.

3. System architecture and circuit implementation

Figure 5 shows the architecture diagram of the proposed DLL, which comprises a digital-controlled delay line (DCDL), a control code generator (CCG), a multiple phase detectors (MPDs) circuit, and a multimode control circuit (MCC). The CCG is composed of a coarse-tuned TDC^[7] for coarse codes generating and a fine-tuned TDC^[8] & bidirectional shift register (BSR) for fine codes generating and tuning respectively. In this design, the proposed DLL has three operation modes: mode1 with four-phase output, mode2 with two-phase output and mode3 with one-phase output. The proposed DLL firstly accomplishes the locking of mode1, and then starts up MCC to realize the locking of mode2 or mode3. Generally, the default operation mode is mode1.

Figures 5(b), 5(c) and 5(d) show the timing diagrams of the proposed DLL working at mode1, mode2 and mode3 respectively. In this design, the locking procedure of the proposed DLL is divided into 3 stages: coarse locking, fine locking and refine locking. In the coarse locking stage, the coarse-tuned TDC generates the coarse codes C[15:0] by measuring the input reference clock period between the two sequential rising edges of the input reference clock, and then completes the coarse locking. In the fine locking stage, the fine-tuned TDC firstly produces the fine codes F[10:1] according to the remaining phase difference between the reference clock CLK_REF and the feedback clock CLK360. Then, BSR loads fine codes F[10:1] and outputs them to the DCDL. The fine locking is completed. After the fine locking, the phase difference between CLK_REF and CLK360 is within the locking range of the DLL in mode1. If the DLL works in mode1, it has been getting locked. If the DLL works in mode2 or mode3, the refined locking stage is needed. In the refined locking stage, MCC retunes the first four fine control codes, F $_{0}$[0], F $_{1}$[0], F $_{2}$[0] and F $_{3}$[0] until the DLL finally gets locked.

3.1 Digital-controlled delay line (DCDL)

Figure 6 shows the block diagram of the DCDL, which is composed of four fine delay units (FDUs)^[8] and four coarse delay units (CDUs)^[7]. The four FDUs are controlled by the same fine control codes F[10:1] and different first control codes, F$_{0}$[0], F$_{1}$[0], F$_{2}$[0] and F$_{3}$[0]. The four CDUs are controlled by the same control codes C[15:0]. The DCDL has three operation modes: mode1 with four-phase output, mode2 with two-phase output and mode3 with one-phase output. The principle of the three operation modes is just the same as in Fig. 2. In mode1, the four first control codes F$_{0}$[0], F$_{1}$[0], F$_{2}$[0] and F$_{3}$[0] are set to the same state. In mode2, F$_{0}$[0] and F$_{2}$[0] are in the same state, and F$_{1}$[0] and F$_{3}$[0] are in the same state. But the two groups F$_{0}$[0]&F$_{2}$[0] and F$_{1}$[0]&F$_{3}$[0] are controlled separately. In mode3, the four first control codes F$_{0}$[0], F$_{1}$[0], F$_{2}$[0] and F$_{3}$[0]are controlled separately.

3.2 Multimode control circuit (MCC)

Figure 7(a) shows the block diagram of the MCC. It is composed of four D-type flip-flops (DFFs), one multiplexer, two AND gates, one select-pass logic circuit controlled by mode-select signals Mode_sel[1:0] and one logic control circuit. The working clock signal CLK of the MCC is co-controlled by CLK_REF, Mode1_locked, Mode2_locked, Mode3_locked and Mode_sel[1:0]. When the DLL works in mode1, the control signal ctrl, which is co-controlled by Mode2_locked, Mode3_locked and Mode_sel[1:0], is set to "0". The signal CLK is also set to "0" accordingly and the MCC does not work. When the DLL works in mode2 or mode3, the signal ctrl is set to "1". The MCC starts to work after the Mode1_locked converts to "1". When Mode_sel[1:0] are "00", "01" and "10", the DLL works in mode1, mode2 and mode3 respectively, and the output signal SEL of the select-pass logic circuit is "X", "0" and "1" respectively. Figures 7(b) and 7(c) show the simplified diagram in mode2 and mode3 respectively.

As mentioned above, the proposed DLL has three operation modes: mode1, mode2 and mode3. In mode1, the clock signal CLK is set to “0”. Thus the MCC does not work and the four first fine control codes, F $_{0}$[0], F $_{1}$[0], F $_{2}$[0] and F $_{3}$[0], are all set to be their initial value “0”. In mode2 and mode3, the DLL can get locked only when the refined locking stage is completed. The refined locking stage is carried out after the fine locking stage. After Mode1's_locked signal goes to “1”, the MCC starts to retune the four first fine control codes, F $_{0}$[0], F $_{1}$[0], F $_{2}$[0] and F $_{3}$[0] until the DLL finally gets locked (Mode2_locked or Mode3_locked signal goes to high). Thus the static phase errors of mode2 and mode3 are reduced to one half and one quarter of mode1 respectively.

4. Measurement results

The proposed multiphase DLL is fabricated in 0.13 $\mu$m CMOS technology. Figure 8 shows the chip micrograph of the proposed DLL. The core area is 0.3 $\times$ 0.4 mm $^{2}$.

Measurement results show that the proposed DLL achieves a locking frequency range of 100 to 400 MHz. All measurements described further are at the square root of this frequency range ( $\sim$ 200 MHz). Figures 9, 10 and 11 show measured static phase errors and histograms of three modes at 200 MHz. The static phase errors of mode1, mode2 and mode3 are -18.2 ps, 11.8 ps and -6.44 ps respectively. Figure 12 shows the measured output jitters of three modes at 200 MHz. The RMS jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps and 2.1 ps respectively, and the p-p jitters are 10 ps, 9.3 ps and 10 ps respectively.

Figure 13 shows the measured static phase errors of three modes versus input frequencies from 100 to 400 MHz. The maximum static phase error in mode1, mode2 and mode3 are 21 ps, 14 ps and 6.4 ps respectively. In Fig. 13, the maximum static phase error in mode 2 is about one half of that in mode1. The maximum static phase error in mode3 is about a quarter of that in mode1. It is obvious that the measurement results accord with the theory. Figure 14 shows the measured peak-to-peak and RMS jitters performance versus the input frequencies of three modes. Table 1 shows the performance comparison of the proposed circuit with previous works. The comparative results show that the proposed DLL can achieve a better static phase error performance than previous works.

5. Conclusion

A multimode DLL with different output phases and static phase error performance is introduced in this paper. By adopting the multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL has three operation modes: mode1 with a four-phase output, mode2 with a two-phase output and better static phase error performance, and mode3 with only one-phase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 $\mu$m CMOS technology and the measurement results show that the static phase errors of mode1, mode2 and mode3 are -18.2 ps, 11.8 ps and -6.44 ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively.

Acknowledgements: Especially, the authors are very thankful to Wei Yuanfeng and Hu Kai for test technical assistance.