Fig. 1.
Basic schematic of the CMOS inverter consisting of a parasitic p-n-p-n structure.
DownLoad:
| Citation: |
Xinhai Yu, Changchun Chai, Xingrong Ren, Yintang Yang, Xiaowen Xi, Yang Liu. Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave[J]. Journal of Semiconductors, 2014, 35(8): 084011. doi: 10.1088/1674-4926/35/8/084011
****
X H Yu, C C Chai, X R Ren, Y T Yang, X W Xi, Y Liu. Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave[J]. J. Semicond., 2014, 35(8): 084011. doi: 10.1088/1674-4926/35/8/084011.
|
Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave
DOI: 10.1088/1674-4926/35/8/084011
More Information
-
Abstract
The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave (HPM) is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS inverters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P=ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value. -
References
[1] Kim K. High power microwave interference effects on analog and digital circuits in IC's. PhD Dissertation, College Park, University of Maryland, 2007[2] Ren Z, Yin W, Shi Y, et al. Thermal accumulation effects on the transient temperature responses in LDMOSFETs under the impact of a periodic electromagnetic pulse. IEEE Trans Electron Devices, 2010, 57(1):345 doi: 10.1109/TED.2009.2034995[3] Kim K, Iliadis A A. Operational upsets and critical new bit errors in CMOS digital inverters due to high power pulsed electromagnetic interference. Solid-State Electron, 2010, 54(1):18 doi: 10.1016/j.sse.2009.09.006[4] Iliadis A A, Kyechong K. Theoretical foundation for upsets in CMOS circuits due to high-power electromagnetic interference. IEEE Trans Device Mater Reliab, 2010, 10(3):347 doi: 10.1109/TDMR.2010.2050692[5] Wang H, Li J, Li H, et al. Experimental study and SPICE simulation of CMOS inverters latch-up effects due to high power microwave interference. Prog Electromagn Res, 2008, 87:313 doi: 10.2528/PIER08100408[6] Kim K, Iliadis A A. Latch-up effects in CMOS inverters due to high power pulsed electromagnetic interference. Solid-State Electron, 2008, 52(10):1589 doi: 10.1016/j.sse.2008.06.041[7] Chen J, Du Z W. Understanding and modeling of internal transient latch-up susceptibility in CMOS inverters due to microwave pulses. http://dx.doi.org/10.1016/j.microrel.2013.07.004, 2013[8] Chen Jie, Du Z W. Device simulation studies on latch-up effects in CMOS inverters induced by microwave pulse. Micro Electron Rel, 2013, 53(3):371 http://www.sciencedirect.com/science/article/pii/S002627141200488X[9] Hwang S M, Hong J H, Han S M, et al. Delay time and power supply current characteristics of CMOS inverter broken by intentional high power microwave. Proceedings of Asia-Pacific Microwave Conference, Bangkok, 2007:1 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=4554704[10] Chai Changchun, Ma Zhenyang, Ren Xingrong, et al. Hardening measures for bipolar transistors against microwave-induced damage. Chin Phys B, 2013, 22(6):068502 doi: 10.1088/1674-1056/22/6/068502[11] Kim K, Iliadis A A. Effects of microwave interference on the operational parameters of n-channel enhancement mode MOSFET devices in CMOS integrated circuits. Solid-State Electron, 2004, 48(10/11):1795 http://adsabs.harvard.edu/abs/2004SSEle..48.1795K[12] Integrated Systems Engineering Corp. ISE-TCAD Dessis Simulation User's Manual. Zurich, Switzerland, 2004:15.195[13] Arora N D, Hauser J R, Roulston D J. Electron and hole mobilities in silicon as a function of concentration and temperature. IEEE Trans Electron Devices, 1982, 29(2):292 doi: 10.1109/T-ED.1982.20698[14] Baliga B J, Ghandhi S K. Electrical and optical properties of tin oxide-gallium arsenide heterojunctions. Solid-State Electron, 1976, 19:739 doi: 10.1016/0038-1101(76)90152-0[15] Brodbeck T, Stadler W, Baumann C, et al. Triggering of transient latch-up (TLU) by system level ESD. 32nd EOS/ESD Symposium, 2010:1 http://ieeexplore.ieee.org/document/5623707/?reload=true&arnumber=5623707&contentType=Conference+Publications[16] Estreich D B. The physics and modeling of latch-up and CMOS integrated circuits. Stanford University, Stanford, CA, Tech. Rep. G-201-9, 1980[17] He Jian, Xu Xueliang, Wang Jian'an, et al. Study on temperature effects on current gain of bipolar transistor. Microelectronics, 2012, 42(2):270(in Chinese) http://en.cnki.com.cn/Article_en/CJFDTOTAL-MINI201202029.htm[18] Liu E K, Zhu B S, Luo J S. Semiconductor physics. 4th ed. Beijing:National Defense Industry Press, 2008:67(in Chinese) -
Proportional views
