Fig. 1.
The PE array architecture
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| Citation: |
Cong Shi, Zhe Chen, Jie Yang, Nanjian Wu, Zhihua Wang. A compact PE memory for vision chips[J]. Journal of Semiconductors, 2014, 35(9): 095002. doi: 10.1088/1674-4926/35/9/095002
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C Shi, Z Chen, J Yang, N J Wu, Z H Wang. A compact PE memory for vision chips[J]. J. Semicond., 2014, 35(9): 095002. doi: 10.1088/1674-4926/35/9/095002.
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Abstract
This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64×64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.-
Keywords:
- vision chip,
- PE,
- memory architecture,
- SIMD,
- edge extraction
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References
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