J. Semicond. > 2014, Volume 35 > Issue 9 > 095009
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SEMICONDUCTOR INTEGRATED CIRCUITS

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

Nan Zhao, Qi Wei, Huazhong Yang and Hui Wang

+ Author Affiliations

 Corresponding author: Zhao Nan, Email:zhaon08@gmail.com

DOI: 10.1088/1674-4926/35/9/095009

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Abstract: This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC). The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signal-to-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.

Key words: pipelined ADC, bootstrapped switch, gradient error, pseudo-random sequence



[1]
Bardsley S, Dillon C, Kummaraguntla R, et al. A 100-dB SFDR 80-MSPS 14-bit 0.35-μm BiCMOS pipeline ADC. IEEE J Solid-State Circuits, 2006, 41(9):2144 doi: 10.1109/JSSC.2006.880590
[2]
Kazutaka H, Furuta M, Kawahito S. A low-power low-voltage 10-bit 100-MSample/s pipeline A/D converter using capacitance coupling techniques. IEEE J Solid-State Circuits, 2007, 42(4):757 doi: 10.1109/JSSC.2007.891683
[3]
Cline D W. Noise, speed, and power trade-offs in pipelined analog to digital converters. Diss University of California, Berkeley, 1995 http://www.eecs.berkeley.edu/Pubs/TechRpts/1995/2908.html
[4]
Francesco C, Monsurró P, Trifiletti A. A model for the distortion due to switch on-resistance in sample-and-hold circuits. IEEE International Symposium on Circuits and Systems, 2006 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=1693701
[5]
Andreas G, Tenhunen H. Performance analysis of sampling switches in voltage and frequency domains using Volterra series. Proceedings of the International Symposium on Circuits and Systems, 2004 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=1328307
[6]
Cai Hua. A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB. Journal of Semiconductors, 2012, 33(11):115013 doi: 10.1088/1674-4926/33/11/115013
[7]
Hafiz O A, Wang X, Hurst P J, et al. Immediate calibration of operational amplifier gain error in pipelined ADCs using extended correlated double sampling. IEEE J Solid-State Circuits, 2013, 48(3):749, 759 doi: 10.1109/JSSC.2012.2230545
[8]
Tseng C J, Chen H W, Shen W T, et al. A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC. IEEE J Solid-State Circuits, 2012, 47(6):1334, 1343 doi: 10.1109/JSSC.2012.2192655
[9]
Taherzadeh-Sani M, Hamoui A A. Digital background calibration of a 0.4-pJ/step 10-bit pipelined ADC without PN generator in 90-nm digital CMOS. IEEE Asian Solid-State Circuits Conference, 2008 http://www.ece.mcgill.ca/~hamoui/FILES/PUBLICATIONS/04708727.pdf?origin=publication_detail
[10]
Boris M, Boser B E. A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J Solid-State Circuits, 2003, 38(12):2040 doi: 10.1109/JSSC.2003.819167
[11]
Sun Kexu, He Lenian. A fast combination calibration of foreground and background for pipelined ADCs. Journal of Semiconductors, 2012, 33(6):065007 doi: 10.1088/1674-4926/33/6/065007
[12]
Daito M, Matsui H, Ueda M, et al. A 14-bit 20-MS/s pipelined ADC with digital distortion calibration. IEEE J Solid-State Circuits, 2006, 41(11):2417 doi: 10.1109/JSSC.2006.882886
[13]
Ryu S T, Ray S, Song B S, et al. A 14-b linear capacitor self-trimming pipelined ADC. IEEE J Solid-State Circuits, 2004, 39(11):2046 doi: 10.1109/JSSC.2004.835823
[14]
Singer L, Ho S, Timko M, et al. A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz. Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2000 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=839681
[15]
Yang W, Kelly D, Mehr I, et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J Solid-State Circuits, 2001, 36(12):1931 doi: 10.1109/4.972143
[16]
Park J B, Yoo S M, Kim S W, et al. A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth. IEEE J Solid-State Circuits, 2004, 39(8):1335 doi: 10.1109/JSSC.2004.831503
[17]
Abo A M, Gray P R. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits, 1999, 34(5):599 doi: 10.1109/4.760369
[18]
Ping C T, Ling T P, Lau G. Analog matching properties process dependency on MIM capacitors. IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2011 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6088329
[19]
ECE1371 Advanced Analog Circuits Lecture 12 Matching and mismatch shaping
[20]
Ye F, Cheng L, Lin K, et al. An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR. Analog Integrated Circuits and Signal Processing, 2010, 63(3):503 doi: 10.1007/s10470-009-9451-2
[21]
Yin Xiumei, Wei Qi, Xu Lai, et al. A low power 12-b 40-MS/s pipeline ADC. Journal of Semiconductors, 2010, 31(3):035006 doi: 10.1088/1674-4926/31/3/035006
[22]
Cai Hua, Li Ping, Cen Yuanjun, et al. A 14-bit 80 MS/s CMOS ADC with 84.8 dB SFDR and 72 dB SNDR. Journal of Semiconductors, 2012, 33(2):025012 doi: 10.1088/1674-4926/33/2/025012
[23]
Choi H C, Yoo P S, Ahn G C, et al. A 14b 150 MS/s 140 mW 2.0 mm2 0.13μm CMOS A/D converter for software-defined radio systems. Int J Circ Theor Appl, 2011, 39:135 doi: 10.1002/cta.v39.2
[24]
Zhao Lei, Yang Yintang, Zhu Zhangming, et al. SHA-less architecture with enhanced accuracy for pipelined ADC. Journal of Semiconductors, 2012, 33(2):025010 doi: 10.1088/1674-4926/33/2/025010
[25]
Kester W. Aperture time, aperture jitter, aperture delay time-removing the confusion. Analog Devices, MT-007 Tutorial, Oct, 2008
[26]
Reeder R, Green W, Shilito R. Analog-to-digital converter: clock optimization. Analog Dialogue 42-02, Feb 2008
Fig. 1.  Architecture of the pipelined ADC.

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Fig. 2.  Simple switch-capacitor sampling circuit.

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Fig. 3.  Typical structure of bootstrapped switch.

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Fig. 4.  HD3 versus input frequency.

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Fig. 5.  Typical 3-bit MDAC architecture.

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Fig. 6.  Layout of sampling capacitors in 3-bit MDAC.

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Fig. 7.  Transfer curves with the injection of PN sequence.

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Fig. 8.  Calibration block diagram of pipelined ADC.

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Fig. 9.  Schematic of PN injection in 4-bit MDAC.

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Fig. 10.  OTA schematic for (a) SHA and (b) Stage2.

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Fig. 11.  Circuit schematic of comparator.

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Fig. 12.  Die photograph of proposed ADC.

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Fig. 13.  FFT spectrum with 19.1-MHz input signal (a) before calibration and (b) after calibration.

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Fig. 14.  Measured SNDR and SFDR versus input frequency.

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Table 1.   Parameters of the bootstrapped switch.

Table 2.   Decoding diagram of reference control signal $D_{i{\rm P, N}}$.

Table 3.   Measured performance summary.

Table 4.   Performance comparison with previous ADCs.
[1]
Bardsley S, Dillon C, Kummaraguntla R, et al. A 100-dB SFDR 80-MSPS 14-bit 0.35-μm BiCMOS pipeline ADC. IEEE J Solid-State Circuits, 2006, 41(9):2144 doi: 10.1109/JSSC.2006.880590
[2]
Kazutaka H, Furuta M, Kawahito S. A low-power low-voltage 10-bit 100-MSample/s pipeline A/D converter using capacitance coupling techniques. IEEE J Solid-State Circuits, 2007, 42(4):757 doi: 10.1109/JSSC.2007.891683
[3]
Cline D W. Noise, speed, and power trade-offs in pipelined analog to digital converters. Diss University of California, Berkeley, 1995 http://www.eecs.berkeley.edu/Pubs/TechRpts/1995/2908.html
[4]
Francesco C, Monsurró P, Trifiletti A. A model for the distortion due to switch on-resistance in sample-and-hold circuits. IEEE International Symposium on Circuits and Systems, 2006 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=1693701
[5]
Andreas G, Tenhunen H. Performance analysis of sampling switches in voltage and frequency domains using Volterra series. Proceedings of the International Symposium on Circuits and Systems, 2004 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=1328307
[6]
Cai Hua. A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB. Journal of Semiconductors, 2012, 33(11):115013 doi: 10.1088/1674-4926/33/11/115013
[7]
Hafiz O A, Wang X, Hurst P J, et al. Immediate calibration of operational amplifier gain error in pipelined ADCs using extended correlated double sampling. IEEE J Solid-State Circuits, 2013, 48(3):749, 759 doi: 10.1109/JSSC.2012.2230545
[8]
Tseng C J, Chen H W, Shen W T, et al. A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC. IEEE J Solid-State Circuits, 2012, 47(6):1334, 1343 doi: 10.1109/JSSC.2012.2192655
[9]
Taherzadeh-Sani M, Hamoui A A. Digital background calibration of a 0.4-pJ/step 10-bit pipelined ADC without PN generator in 90-nm digital CMOS. IEEE Asian Solid-State Circuits Conference, 2008 http://www.ece.mcgill.ca/~hamoui/FILES/PUBLICATIONS/04708727.pdf?origin=publication_detail
[10]
Boris M, Boser B E. A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification. IEEE J Solid-State Circuits, 2003, 38(12):2040 doi: 10.1109/JSSC.2003.819167
[11]
Sun Kexu, He Lenian. A fast combination calibration of foreground and background for pipelined ADCs. Journal of Semiconductors, 2012, 33(6):065007 doi: 10.1088/1674-4926/33/6/065007
[12]
Daito M, Matsui H, Ueda M, et al. A 14-bit 20-MS/s pipelined ADC with digital distortion calibration. IEEE J Solid-State Circuits, 2006, 41(11):2417 doi: 10.1109/JSSC.2006.882886
[13]
Ryu S T, Ray S, Song B S, et al. A 14-b linear capacitor self-trimming pipelined ADC. IEEE J Solid-State Circuits, 2004, 39(11):2046 doi: 10.1109/JSSC.2004.835823
[14]
Singer L, Ho S, Timko M, et al. A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz. Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2000 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=839681
[15]
Yang W, Kelly D, Mehr I, et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J Solid-State Circuits, 2001, 36(12):1931 doi: 10.1109/4.972143
[16]
Park J B, Yoo S M, Kim S W, et al. A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth. IEEE J Solid-State Circuits, 2004, 39(8):1335 doi: 10.1109/JSSC.2004.831503
[17]
Abo A M, Gray P R. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J Solid-State Circuits, 1999, 34(5):599 doi: 10.1109/4.760369
[18]
Ping C T, Ling T P, Lau G. Analog matching properties process dependency on MIM capacitors. IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2011 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6088329
[19]
ECE1371 Advanced Analog Circuits Lecture 12 Matching and mismatch shaping
[20]
Ye F, Cheng L, Lin K, et al. An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR. Analog Integrated Circuits and Signal Processing, 2010, 63(3):503 doi: 10.1007/s10470-009-9451-2
[21]
Yin Xiumei, Wei Qi, Xu Lai, et al. A low power 12-b 40-MS/s pipeline ADC. Journal of Semiconductors, 2010, 31(3):035006 doi: 10.1088/1674-4926/31/3/035006
[22]
Cai Hua, Li Ping, Cen Yuanjun, et al. A 14-bit 80 MS/s CMOS ADC with 84.8 dB SFDR and 72 dB SNDR. Journal of Semiconductors, 2012, 33(2):025012 doi: 10.1088/1674-4926/33/2/025012
[23]
Choi H C, Yoo P S, Ahn G C, et al. A 14b 150 MS/s 140 mW 2.0 mm2 0.13μm CMOS A/D converter for software-defined radio systems. Int J Circ Theor Appl, 2011, 39:135 doi: 10.1002/cta.v39.2
[24]
Zhao Lei, Yang Yintang, Zhu Zhangming, et al. SHA-less architecture with enhanced accuracy for pipelined ADC. Journal of Semiconductors, 2012, 33(2):025010 doi: 10.1088/1674-4926/33/2/025010
[25]
Kester W. Aperture time, aperture jitter, aperture delay time-removing the confusion. Analog Devices, MT-007 Tutorial, Oct, 2008
[26]
Reeder R, Green W, Shilito R. Analog-to-digital converter: clock optimization. Analog Dialogue 42-02, Feb 2008

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    Received: 29 January 2014 Revised: 19 February 2014 Online: Published: 01 September 2014

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      Article Navigation >  Journal of Semiconductors  > 2014  >  35(9): 095009
      Nan Zhao, Qi Wei, Huazhong Yang, Hui Wang. A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR[J]. Journal of Semiconductors, 2014, 35(9): 095009. doi: 10.1088/1674-4926/35/9/095009 ****N Zhao, Q Wei, H Z Yang, H Wang. A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR[J]. J. Semicond., 2014, 35(9): 095009. doi: 10.1088/1674-4926/35/9/095009.
      Citation:
      Nan Zhao, Qi Wei, Huazhong Yang, Hui Wang. A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR[J]. Journal of Semiconductors, 2014, 35(9): 095009. doi: 10.1088/1674-4926/35/9/095009 ****
      N Zhao, Q Wei, H Z Yang, H Wang. A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR[J]. J. Semicond., 2014, 35(9): 095009. doi: 10.1088/1674-4926/35/9/095009.
      shu

      A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

      DOI: 10.1088/1674-4926/35/9/095009

      • Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

      Funds:

      the National Science Foundation for Young Scientists of China 61306029

      the National High Technology Research and Development Program of China 2013AA014103

      Project supported by the National Science Foundation for Young Scientists of China (No. 61306029) and the National High Technology Research and Development Program of China (No. 2013AA014103)

      More Information
      • Corresponding author: Zhao Nan, Email:zhaon08@gmail.com
      • Received Date: 2014-01-29
      • Revised Date: 2014-02-19
      • Published Date: 2014-09-01

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