1. Introduction

Due to the demand for increased integration,device geometries have scaled from submicron,to deep submicron,and now to sub-100 nm. In modern deep-submicron technology the total ionizing dose (TID) hardness is inherently high and single-event effects (SEE) are major problems for space CMOS microelectronic components^[1]. SEEs in microelectronics occur when highly energetic particles (e.g.,protons,neutrons,alpha particles,or other heavy ions) strike sensitive regions of a microelectronic circuit. Depending on several factors,the particle strike may cause single event transient (SET),single event upset (SEU),or even single event latch (SEL). There are many solutions to increase SEL immunity. Triple well (TW) or deep N-well (DNW) and guard rings^[2] are implementable on a standard commercial technology and allow reaching the SEL threshold linear energy transfer (LET) level $\sim$ 60 MeV$\cdot$cm$^{2}$/mg and more.

Rapidly shrinking technology feature size,increasing operating frequencies and lower power voltages have caused single event soft errors to be one of the key reliability issues in advanced ICs. The critical charge $Q_{\rm cri}$ (quality control reliability investigation),i.e.,the minimum charge required to upset a storage cell deceases as semiconductor devices scale down. Hence,even an incident ion that deposits a small amount of energy can cause an SEU. What is more,reduced distances between transistors make multiple transistors vulnerable to a single ion strike,resulting in multiple-cell upsets. Thus,aggressive process scaling makes the probability of multiple-cell upsets (MCU) greater,as shown in Figure1Π^{[3, 4, 5, 6]}.What is more,multiple bit upset (MBU) and MCU are both related to upsets induced by charge sharing; in the following paper,MBU would be used to present such an effect.

Besides traditional SEUs in storage cells,charged particles may also induce SETs. As device geometries have scaled to deep submicron,circuits became sufficiently fast and single events error rates became dominant in such circuits using SEU hardened static-latch cells. As features sizes continue to decrease below 100 nm,digital single event transient (DSET) induced error rates will soon dominate the soft error rate of even unhardened latch designs^{[7, 8, 9, 10, 11, 12, 13, 14, 15]}. Increasing number SETs are also observed in analog circuits. SET are becoming the dominant single event soft error effect in heavy ion environments. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV$\cdot$cm$^{2}$/mg,and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100 nm technology node. Because this corresponds to the maximum LET of $\alpha$-particles and they are one of the most abundant reaction products for both proton and neutron interactions in Si,this may portend a large increase in error rates due to SETs at 65nm for proton-rich space environments and terrestrial neutron environments. Thus SET is becoming more of a challenge for advanced circuit design^{[16, 17, 18]}.

As technology feature sizes decrease,single event upset,and multiple bit upset,single event transient,including digital single event transient and analogue single event transient (ASET),dominate the radiation response of microcircuits. The remainder of the paper is organized as follows: Section 2 presents a brief historic overview of SEU and SET research; the basic mechanism of SEE is described in Section 3; Sections 4 and 5 describe SEE effects and mitigation techniques respectively. Finally,Section 6 concludes the paper.

2. Historical overview

In 1975 Intel described a-particle induced soft error,and space programs began reporting on-orbit occurrence of single event upsets. In 2003,Dodd and Massengill published a paper that reviewed the history of single-event effects^[19]. Single-event multiple bit upsets were briefly discussed in it with a statement that these effects may become more prevalent in advanced technologies. This review contains one additional charge collection mechanism,well-collapse source injection,which was postulated by Woodruff and Rudeck^[20],was demonstrated in a model and test data by Olson et al. in 2005^[21],and explained by Black et al. in 2008^[22]. As a result,multiple-node charge collection has always been present in microelectronics. A major change that we have observed in the last ten years is that more research is focused on multiple-node effects and that computing resources are enabling more transistors/devices to be simulated in a fully three-dimensional domain^[23]. As a result,we are better able to predict the occurrence of new single event effects,such as pulse-quenching^{[24, 25]}.

The earliest paper from the radiation effects community on single event transients was published in 1983^[26]. The experimental study of Friedman et al.^[27] concluded that,at that time,the SET issue was more of a curiosity than a critical failure mode. A few years later,experimental measurements under heavy ion irradiation reported significant contributions of single event transients ^{[28, 29]}. Findings resulted in the general rule that SET sensitivity is expected to increase with circuit frequency and deposited charge^{[30, 31, 32, 33]}. In 1997,Baze et al. established the general conditions for the dependence of transient propagation in a logic chain on its initial width and magnitude^[34]. They stated that ``as a general rule,only pulses wider than the logic transition time of a gate can propagate through the gate without attenuation''. SETs have been observed in analog and mixed-signal integrated circuits in space,including operational amplifiers and voltage comparators^[35],and optocouplers and transceivers^[36]. Ground tests have shown that SETs in some of these circuits can be relatively long (hundreds of picoseconds to microseconds),increasing the probability of producing erroneous signals in follow-on circuits^[37]. Several papers confirmed that the newer CMOS technologies (0.25 $\mu$m and below) were quite sensitive to SETs^{[38, 39, 40, 41, 42]}. In 2007,experiments demonstrated a newly-observed phenomenon,propagation-induced pulse broadening (PIPB)^{[43, 44, 45]}. It was modeled in 2008 ^{[46, 47]} as a function of the technology,gate design and bias history. Other studies^[48] also showed a significant pulse quenching due to charge sharing between the struck node and the following gates. Papers discussing ASET always concentrate upon modules like PLL and AD^{[48, 49, 50, 51, 52, 53, 54, 55, 56]}. These modules with a clear configuration and comprehensive applications as well as strong representations are pivotal circuits in analog/mixed signal designs. While those high speed and high performance circuits are especially sensitive to radiation effects,which have become a keystone and difficulty on RHBD. Although tools like TCAD can realize accurate SET simulation ^{[48, 57]},the more universal method is simulation based on fault injection because of the high complexity of analog circuits ^{[58, 59]}. Studies have been done recently to model and simulate ASET on behavior level about analog circuits. The circuit represented by PLL has achieved behavioral level modeling consistent with SPICE simulation results^[60].

3. Single-event effects

3.1 SEU effects

Through the use of some new material,the soft error rate will be largely decreased. For example,by using the strained devices,the carrier mobility increases thereby increasing the drive current^[25]. Experiment results show that the total soft error rate of both the single-bit upset rate and multi-bit upset rate decreases by approximately 50% with strain. Besides,the presence of high-$Z$ materials,like tungsten,can increase the SEU and MBU cross sections of high critical charge devices exposed to the terrestrial neutron environment because of interactions with high energy neutrons^[61]. Another new material called borophosphorosilicate glass (BPSG) layer,commonly used in complementary metal oxide semiconductor (CMOS) SRAM-memory,triggered the production of a significant number of Li nuclei and alpha particles when exposed to neutrons^[62]. These highly ionizing Li and He ions produce a significant ionization charge in a small volume that is able to induce a current pulse in memory cells changing their logical state. Furthermore,Intel's transition from a conventional SiO$_{2}$ bulk CMOS to a high-$k$ $+$ metal gate (HK $+$ MG) technology has neither impacted the SRAM scaling trend nor the SRAM single- and multi-bit soft error trends in a negative fashion^[63]. On the other hand,process variations has a strong impact on radiation-induced soft errors,results indicate that the peak-to-peak upset probability differences show a difference of 73.9% in threshold voltage,122.3% in electrical gate oxide thickness and 66.6% in length variation. Similarity,temperature could also be a factor to influence the single event effects. The temperature's effect to the LET$_{\rm th}$ of the active cell is negligible,the LET$_{\rm th}$ of the passive cell decreases significantly in the whole temperature range^[64]. This is because the charge sharing collection increases and upset voltage decreases with temperature rising. While other facts,like negative bias temperature instability (NBTI) do not have a large impact on the single-event upset rate calculations.

The charge sharing and collection between nodes induced by incident particles and the mechanism of cell upsets are discovered. The priority reason is due to energetic particle interaction with the device structure. The interaction results in direct ionization or secondary particles that traverse the device leaving a plasma region of electron-hole pairs in its wake. New technology brings our attention to neutrons,which can indirectly induce soft-error through a reaction with atomic nucleus of transistor materials,as shown in Figure2. The nuclear reaction generates charged secondary particles like protons,alpha particles and heavy ions. The charged particle generates electron-hole pairs by direct ionization on the particle track and deposits charge. The generated charge is collected to drain by drift and diffusion,and causes a soft-error. In recent 65 nm to 25 nm technologies,it is reported that direct ionization due to secondary alpha particles are a major contributor to the neutron soft-error-rate (SER) in the terrestrial environment^[65]. On the other hand,in low voltage SRAM,direct ionization from secondary protons can be a major contributor^{[65, 66, 67]},because the low voltage operation reduces critical-charge ($Q_{\rm c})$. Reference ^[67] demonstrated that low energy protons contribute to SER by direct ionization and the cross-section of low energy protons (MeV) is three orders of magnitude larger than that of high energy protons (MeV). The impact of a proton on SER is also investigated. In the space environment^[68],direct ionization from protons is a major contributor to the total SER in the ISS orbit and geosynchronous (worst day) orbit. Returning to the terrestrial environment,it is demonstrated that the number of generated secondary protons is one or two orders of magnitude larger than the number of alpha particles^[66] (shown in Figure3). The direct ionization from a proton could dramatically increase neutron SER of ultra-low voltage SRAM.

3.2 SET effects

A large amount of research has been performed measuring SET pulse widths in deep submicron bulk technologies. Narasimham et al. in 2007 measured SET widths over 1 ns in a 90-nm technology^[77],and in 2009 Cannon et al. presented data in a 90-nm technology showing that measured SET widths were consistently less than 400 ps^[78]. Heavy ion test from Actel indicated that all the SET pulse widths were shorter than 250 ps till an LET of 83.1 MeV$\cdot$cm$^{2}$/mg in 65 nm technology^[79]. However,significant differences in the maximum SET width between the 130 nm,90 nm,65 nm technology nodes exist in Reference ^[80]. The maximum SET widths for an LET of 60 measured in the 65-nm test structure are only 250 ps whereas in the 130-nm and the 90-nm test structures the maximum SET widths are near 1500 ps. The difference between simulation and test is because the PIPB effect has not been considered in the simulation. Those differences between different test results are largely due to different implements of test chips,as SET pulse width can be largely effected by various factors,which will also be discussed later.

In most test structures,it is assumed that the SET width is preserved when traversing a chain of identical cells. This assumption has driven the design of test structures towards long chains of inverters to increase the SET capture cross-section. However,work ^{[41, 42, 44, 46, 81, 82, 83]} has shown that transient signals can widen as they propagate through a combinational logic chain. The PIPB effect is well known in SOI^[84]. It can also exist in bulk technologies^[42]. Technologies and designs prone to floating body effects are particularly sensitive to PIPB. Measured broadening rate ranges from 1 ps per gate in a 90 nm to almost an order of magnitude less in 65 nm technology^[80]. Pulse broadening can be attributed to the speed difference between the rising and the falling edge and many researchers have analyzed its dependencies on various factors ^{[80, 84, 85]}. The worst case for PIPB is at low frequency,when the body potential of transistors reaches a quasi-static bias state before the SET propagation^[44]. PIPB typically increases when the supply voltage is reduced ^{[82, 85, 86]} and high doping levels result in large PIPB^[87]. As for the impact of gate design,NAND gates have a lower cross-section than the inverter. A direct relationship has been observed between the PIPB effect and both the node capacitance (capacitive loads) and the transistor size ^{[42, 44, 46, 88]}. The dependencies of the SET characteristics on the input patterns,propagation paths,pulse polarity,diverging paths,and re-converging paths are investigated in Reference ^[89].

Pulse quenching is a direct result of single event charge sharing,discovered in 2009 at the 130-nm technology node. Pulse quenching is the name given to the phenomenon of single event pulse width reduction due to delayed charge collection (via charge sharing)^[24]. There are two basic conditions for pulse quenching to occur. First,the technology must have a propensity for charge sharing and the second requirement is that the charge collection time constant associated with charge sharing must be on the same order as the gate-to-gate electrical propagation delay of the logic. Figure4 shows a pulse quenching event. Analysis by Ahlbin et al. experimentally verified pulse quenching in 65-nm CMOS inverter chains^[90]. Experimental results indicate that the effects of pulse quenching are more prevalent in the common n-well design compared to the separate n-well design. Experimental data for a normal incidence ion with an LET of 58 MeV$\cdot$cm$^{2}$/mg shows a 42% reduction in the average SET pulse width and an 86% reduction in the number of events measured between the common n-well design and the separate n-well design. Pulse quenching has also explained a counter-intuitive weak dependence of SET pulse widths on incident particle energy in sub-100-nm CMOS technologies^[91] and it has been associated with an observed saturation of SET rates with dimensional scaling^[80].

Multiple single-event transients (MSETs) in a circuit result when multiple transistors collect charge from a single ion hit (termed charge sharing). As transistor density increases with each new scaled technology,the probability of a single ion causing multiple transistors to collect charge increases ^{[92, 93]}. A different SET characteristic has been observed in sub-100 nm bulk technologies,the double-pulse-single-event transient (DPSET)^[94]. This may result into two separate SETs that may propagate through the circuit. Digital SETs in 65 nm bulk CMOS inverter strings show that angled particle strikes can cause double-pulse-single-event transients (DPSETs). The cross section of DPSETs is directly related to the particle angle of incidence. As the angle of incidence increases,the cross-section of DPSETs increases. Besides being induced by heavy ion,MSET could also be induced by other particles. MSET evaluations based on device and circuit simulation were reported^[95]. Measurement of neutron induced MSET (single event multiple transients) was reported in 2011. The measurement result of the 65 nm CMOS test chip showed that SMET ratio increases as decreasing the supply voltage and biasing the body in the reverse direction. It is also shown that the occurrence tendency of spatial patterns of MSETs and no MSET observation across three cells in the vertical direction due to the well boundary^[96].

Previous work for SET characterization showed that SET pulse width varies with a lot factors,including layout,temperature,and circuit design. A lot of works illustrate how the layout may affect the SET effect of a design. Heavy ion experiments on 65 nm bulk CMOS inverter chains demonstrate that SET pulse width and cross-section are reduced in the horizontal placement compared to the vertical placement due to stronger pulse quenching^[97]. Heavy ion results from a 90 nm process show that inverters with the smallest percentage of n-well contact area within an n-well produced the longest and most frequent SETs. As the percentage of n-well area contacted increases above 2%,the pulse width and number of SETs levels off^[98]. Pulse width measurements indicated that the increased transistor density reduced the SET cross section by up to 70% while barely affecting the distribution of pulse widths^[99]. In digital logic circuit-level effects such as SET pulse quenching are heavily dependent on the placement of specific transistors,but all transistors in a high-density layout are subject to the effects of charge sharing with proximate transistors^[100]. The combined effects of temperature and SETs are also strongly dependent on the technology (bulk or SOI) used to fabricate the circuits,and the SET testing conditions. Experimental measurements and TCAD simulations showed that increased temperature leads to lengthen SET pulses in advanced bulk technologies ^{[83, 101, 102, 103]}. For this 90-nm bulk device,average values of measured SET pulse widths increased by as much as 37% when temperatures increased from 25 to 100 ℃. This effect was primarily attributed to an increase in the bipolar amplification effect with increased temperatures^[104]. Measurement results obtained from a 65 nm technology using heavy-ions showed different dominant mechanisms for charge collection for P-hits and N-hits. For low LET particles,the conventional drift and diffusion charge collection mechanisms lead to slightly longer pulse widths for N-hits,but for high LET particles,charge amplification by the parasitic bipolar effect leads to longer pulse widths for P-hits^[105]. Decreased supply voltage leads to increased SET pulse width,which is mainly caused by an increasing transition time of the latter edge of the SET^[106]. When it comes to logic gates,NAND and NOR gates have higher SET cross section and generate wider pulses than inverters. Drive strength generally dominated the SET response at low LET and large LET measurements responded more strongly to the sensitive area^[107].

4. Single event soft error mechanism

A single event effect is simply any effect on a microelectronic integrated circuit (IC) that is the result of energy-deposition by a single incoming ionizing particle. Two interested single event effects are SET,which is a radiation-induced current or voltage pulse occurring at a circuit node and SEU,which is a radiation-induced change in static logic state. An SEU is the manifestation of an SET on a specific sensitive circuit node. We will describe the fundamental mechanisms that produce SEUs and SET.

When a charged particle passes through a reverse-biased junction it results in a transient current and thus charge collection at the struck electric node. It has been shown that the transient current consists of a fast drift and ``funnelling'' component and a slower contribution from charge diffusion in the silicon substrate. Bipolar amplification may also further enhance the transient current,depending on the device structure and the exact position of the particle strike ^{[20, 69, 70, 73]}. The transient current is fundamentally transformed when the transistor is integrated in a chain of logic cells ^{[71, 2]}. After a short-duration current peak,the single event current is governed by the depressed drain voltage and the compensating transistor drive current. The result of this dynamic interaction of the node voltage and the compensating currents is a characteristic SET current equilibrium or "plateau". The parasitic bipolar transistor is formed by the drain,acting as the collector,the channel,acting as the base and source regions,acting as the emitter,as shown in Figure5. For the parasitic bipolar structure,decreasing gate length would increase the bipolar current gain^[74].

A sufficiently strong pulse will reverse the cell state,resulting in SEU. However,if the particle strike occurs in combinational logic,the collected charge may induce a voltage transient at the struck node,i.e.,an SET. This SET may propagate and induce an error in a memory element,if the following four conditions are fulfilled: (1) the SET is generated at a sensitive logic node,(2) it propagates down an open logic path and arrives at a latch or other memory element,(3) it arrives with sufficient amplitude and duration to change the memory state,and (4) it arrives during the cell "window of vulnerability".

5. Mitigation approaches

There has been a great deal of work on radiation hardened design approaches and mitigation techniques,which are discussed for SEU hardening and SET hardening respectively.

5.1 SEU mitigation

Design hardening is a main method to deal with both SEU and MBU. Design hardening includes cell circuit hardening and layout hardening.

The way of circuit hardening is to add the pulse mitigation and nodes redundancy. There are typical improvements according to different cells. For example,the SRAM memory cell has several classic cell architectures as 6T $+$ RC structure,DICE memory cell,11T memory cell and 13T memory cell etc.

The use of resistors and capacitors (RC) to harden SRAM cells against SEUs has long been a common radiation-hardening practice. Use of deep trench capacitors (DTC) is a common option,and is an approach to implement a hardening capacitor in SRAM cells. The high aspect ratios attainable with advanced processing enable attractive capacitance per unit area. A 6T1C1R cell in 90 nm DTC technique is adapted in Figure6. Due to its asymmetric design and characterizations of DTC,it indicates a strong dependence on hit angle,with normal hits being the worst case.

A dual interlocked cell (DICE),as shown in Figure7,is another solution. Unfortunately,they are vulnerable to SEU in sub-100 nm technologies due to the small distance between two neighboring sensitive volumes. Nevertheless,2-$\mu$m nodal spacing of all sensitive pairs helps to improve the SEU tolerance of such cells^[108]. Figure8 shows 11T cell architecture adds a gate controller based on the 6T circuit. It improves the cell's ability against SEU through mitigating or cutting down the pulse generated by SEU. But a single ended SRAM cell operates correctly when writing "0" as data,but it may encounter problems when writing "1". The 11T memory cell is unable to restore the state of the node when a multiple node upset occurs. The 13T memory cell is proposed to improve the multiple node upset tolerance. Its design is shown in Figure9. We can see that multiple node upset tolerance of the 13T cell is improved significantly (shown in Figure10(a)). The area under the curve is significantly increased compared with the 11T cell,making it comparable to the area of the DICE cell,shown in Figure10(b).

With the distance increasing between latches,the rate of MBU and SEU decreases exponentially. The experimental results have proved the well contact placed between two latches can mitigate MCU. Researchers propose a technique that mitigates multi-bit-upset without performance degradation by applying well-slits. The area overhead in an MBL macro for processor design,which includes a clock buffer and a checker,is only 5.4% in a 28 nm technology. A sixty-hour accelerated neutron irradiation test observed no MBUs with well-slits,the layout is shown in Figure11. The inserted well-slits isolate wells of each latch for preventing charge diffusion and parasitic bipolar action. This well-slit technique can be applied to any bulk CMOS technologies without process customization,and MBU mitigation can be achieved only by design modification and consequently with low cost^[109].

5.2 SET mitigation

To eliminate the effects of SET pulses,redundant circuits,either spatial or temporal,are employed. Mavis and Eaton presented temporal sampling as a DSET hardening technique^[110]. Figure12 shows the basic topology of temporal sampling. Only legitimate signals of sufficient pulse length appear simultaneously at all three DFFs and are voted through the temporal latch. Any signal (SET) shorter will be corrected by the majority. In 2003,Mongkolkachit et al. proposed a method of combined temporal filtering with spatial redundancy to block DSETs of a duration shorter than the expected synchronous digital signals^[111]. Based on the mechanism of filtering SET,a low pass filter (LPF) has been proposed and discussed^{[112, 113, 114, 115, 116]}. One of these techniques,as shown in Figure13,led to the name "SET guard gates." Similar temporal/spatial redundancy techniques have been implemented by Nicolaidis^[117]. Guard gating DSET hardening techniques have been integrated into static SEU-hardened latch designs,such as the DF-DICE design of Naseer et al.^[118] and SET-SEU-RHBD flip-flop of Uemura^[119]. The later flip-flop is proposed with an LPF using a C-element with dual transmission on 45-nm technology. The flip-flop can protect 90% of SEU and 52 ps SET pulse with low penalties. While these inserted SET filters introduce a long delay,regardless of whether an SET is occurring,this will increase the setup time of a latch/flip-flop and reduce the useful operating frequency. Full spatial redundancy has also been implemented for DSET mitigation,for example,self-voting dual-modular-redundancy techniques ^{[120, 121]} and techniques using redundant combinational logic circuits ^{[122, 123]}.

Large single-stage drivers were deemed as another effective way to significantly mitigate transients^{[124, 125, 126, 127]},while there were also studies which pointed out that the transistor symmetric sizing technique is able to degrade the transient pulse due the lower LET of the particle,but increase the transient pulse amplitude and duration making the SET effect even worse or high energy particles^[127].

In recent years,new RHBD methods were introduced to mitigate SET effects,aimed to cope with the short comings of conventional solutions by adding very little redundancy to the system and improving the total overhead penalties. In 2010,a DICE-based flip-flop with CK SET discriminator was designed and evaluated^[128]. For the normal incident ions,the flip-flops indicated good SEU/SET immunity. At the tilt angle of 90$^\circ$,SEU sensitivity was confirmed with relatively low LET ions. Another flip-flop with SET suppressor was proposed in the same year,which mitigates SETs by adjusting the clock edge timing^[129]. The SET suppressor only increases very little flip-flop delay when no SEU occurs near the capturing clock edge. Simulation results demonstrate that the proposed scheme has better performance than SET filters. What is more,a redundancy based clock buffer is designed for mitigating an SET of the clock in latches. If noise occurred on one split clock buffer,retention data of the latch is not upset; it can mitigate almost neutron induced SET in local clock^[130]. In 2011,an approach using a pair of cross-coupled inverters at the data input of sequential elements,acting as a weak latch to mitigate the SET problem is published. SET pulse widths smaller than the added delay will be filtered out and ones close to this delay decreased^[131]. SET recovery techniques have been studied as another way to mitigate the SET effect. A recovery system based on an extra flip-flop as a back-up for the principal flip-flop and SET detectors were implemented. Simulation results show it has good fault-tolerance for pulses of a duration up to 500 ps^[132].

Different types of analog circuits produce different injure and effect after radiation. A common way to study nanometer ASET is based on the specific sensitive structure of the circuit to obtain the optimal hardening ability and performance as well ^{[48, 50, 51, 133, 134]}. With the reduction of process size,an SET quenching effect is shown,in company with the several basic characteristics and features of the analog circuit such as a different structure,matching design criteria and common centroid layout design,making charge sharing become a useful and extensive scheme in the circuit level and layout level of nanometer scale design ^{[57, 134, 135, 136]}. Circuit-level reinforcement based on an additional current mirror circuit to enhance the charge sharing effect to compensate transient charge caused by a single-particle. Generally,the reinforcement purpose achieved by increasing the circuit will introduce new sensitive areas,increase static power and be limited by the frequency response of the circuit. A paper^[135] proposed a circuit level hardened technology that provided up to 66% reduction in amplitude and 62% reduction in the duration of the circuit's worst case response following a 60 degree 40 MeV$\cdot$cm$^{2}$/mg strike combined common centroid layout techniques.

PLL is discussed as an example for ASET hardening. Through a large number of simulations and experiments,the most sensitive analog modules of SET are the voltage controlled oscillator (VCO) and charge pump (CP). A number of RHBD technologies have been proposed to harden the modules. An effective technique is using a voltage-based charge pump (V-CP) shown in Figure14(b) instead of the current-based charge pump (C-CP) shown in Figure14(a)^[137]. Compared with C-CP,there are less sensitive nodes,faster charge leakage and injection and less locked time of PLL. Besides,the series R1 insulates the CP and the VCO and reduces the influence from CP to VCO control voltage. There are several shortcomings of the V-CP,such as more jitter and nonlinear problem. Another method is using a complementary current limiter (CCL) to limit SET induce current. The CCL consist of a pair of complementary amplifiers and a pair of complementary transistors for limiting current. It has being proved that the CCL could reduce fluctuation of control voltage and recovery time (shown in Figure15). The VCO become more sensitive to SET^[138]. Keeping the frequency and adding the order of the VCO raises current and reduces the SET-induced problem essentially. The traditional redundancy measurements are still effective RHBD technology. The structure (shown in Figure16) using an $M$-path redundancy bias circuit to reduce the SET-induced problem for the $V_{\rm pbias}$ and $V_{\rm nbias}$^[139]. The high-energy particle-induced effect to the bias voltage could be reduced to 1/$M$ compared to the non-RHBD structure. The TMR^[140] (shown in Figure17) VCO maximum increase opposes the capability of particle strike,reduces the SET-induced problem to the level of background noise. However,performance improvement by the TMR strategy costs more layout area,more power dissipation and lower frequency,and the decision circuit will bring new sensitive nodes and reduce the RHBD effect.

Despite the circuit design schemes that have been proposed to reduce the threat of SETs to ICs,other attempts to reduce the initial SET pulse width at the struck logic cell also appear promising. The use of high-density well contacts and biased guard bands,which are also well contacts that encircle the individual transistors to sink excess charge away from critical nodes,has been shown to significantly affect SET properties^{[141, 142, 143, 144, 145, 146]}. Heavy-ion test results indicate guard bands,along with high density well contacts,helps eliminate $>$70% of SETs longer than 1 ns in a 130-nm process^[146]. Previous works have also discussed the use of guard bands (also called guard rings) and well contacts to maintain the well potential during a strike and thus reduce SET pulse widths by mitigating the parasitic bipolar effect in PMOS devices residing in the n-well.

However,for NMOS devices in the p-substrate,charge collection is not enhanced by the parasitic bipolar transistor and guard rings are less efficient in reducing drift and diffusion charge collections,which are dominant in NMOS transistors. Guard drains are another layout technique,which are reversed biased diodes placed near the drain regions in order to minimize the charge collected by the hit device and charge sharing between nodes (shown in Figure18 in comparison with the guard ring). The guard drain regions act as a secondary charge collection region and collect some of the deposited charges thus reducing the charge available for collection by the hit device. Heavy ion test results from 180 nm and 130 nm test chips indicate that guard rings are better for PMOS devices,while guard drains are better at mitigating charge collection for NMOS devices^[147].

Conclusions made about the effectiveness of the above techniques do not take into account the electrical relationship among multiple transistors collecting charge for combinational-logic circuits,where transistors in close proximity are usually electrically related,such SETs interfere with each other to alter the overall SET pulse observed at the out put of the circuit^[150]. When the electrically coupled nodes collect charge simultaneously,pulse quenching effects reduce the overall SET pulse width partially or completely,resulting in decreased SE vulnerability ^{[24, 90, 148, 149]}. Experimental observations at the 32-nm and 65-nm technology nodes ^{[90, 151]} have demonstrated that layout can be exploited to modulate single-event charge sharing and,by extension,pulse quenching. Other recent papers have analyzed the pulse-quenching effect in relation to mitigation,or reduction of charge sharing ^{[24, 152]}. Utilizing these new findings provides additional means to reduce SET pulse width^[153]. A contrarian layout technique by introducing one extra drain diffusion into a cell output buffer transistor to intentionally promote charge sharing between transistors and quench the voltage pulse on the output. Furthermore,the mitigation improves with technology scaling,since the technique exploits charge sharing. These results will allow designers to reduce cumulative SE vulnerability of a cell library with an area penalty of 10-40%. TCAD simulations show as much as 60% reduction insensitive area and 70% reduction in pulse width for some logic cells.

In recent years,there are also layout techniques based on different mechanism of p-hit and n-hit. A layout technique on source isolation to mitigate p-hit SET is published in 2012,which utilized shallow trench isolation (STI) to isolate PMOS in the same active area. Based on 90-nm twin-well CMOS technology,the simulation results indicate that the source isolation technique can significantly reduce SET pulse width^[154]. As for the n-hit,a source-extension layout technique is proposed based on the mechanism of a parasitic reversed bipolar effect in the n-hit SET production process,which is found through three-dimensional (3D) mixed-mode technology computer-aided design (TCAD). The source-extension technique used two half-sided parallel NMOSs instead of the traditional layout,so that the drain area is reduced by half and the source is split and located on two sides of the drains. Based on 65 nm CMOS technology,3D TCAD simulations and heavy-ion experiments indicate that the source-extension technique can efficiently reduce n-hit SET pulse widths^[155].

A radiation hardened by the design technique based on charge sharing in the analog circuit includes layout and circuit reinforcement. General principle of the layout stage are that the drains of the devices are placed as close as design rules allow and when applicable,letting the layout achieve a common centroid and matching configuration,maximizing the same possibility of the ion bombardment effect on the differential pair,to cancel part or all of the transient effects. It is note worthy that the same minimum distance of the drain in a different drain-source display mode will get a different anti single event transient ability^[134] take the layout of a mirrored pair N9/N10 in the cascade stage (shown in Figure19) of a folded cascade operational amplifier (Figure20 shows the schematic below) for example. Laser experiments were performed to verify the transient effect of a single event respectively on the cascade stage of a folded-cascode operational amplifier by the constitution of three kinds of layout configuration. The results (as shown in Figure21) showed that the DCC layout technology which completely minimized the drain terminal distance in the centroid expressed a minimum sensitivity than the CC layout technology which only minimized the drain on the same side distance. In the combination of settling time threshold and three kinds of laser energy relationships,the DCC layout technique achieved sensitive area reductions ranging from 41% to 95% with an overall area penalty of less than 1%^[134]. Furthermore,a matched layout is also beneficial even when a common centroid layout approach is not an option^[57].

The experiment has investigated neighboring junctions competing for ion-generated charge and by using different excitation sources,can obtain different probabilities that charge sharing events occur^[136]. The charge collection was investigated by multiple junctions using broad beam heavy-ion and backside laser current transient measurements,and concluded the probability of charge sharing using TPA is 25% higher than it is for heavy-ions.

6. Conclusion

As technology feature sizes decrease,single event upset and multiple bit upset effects,and single event transients including the digital single event transient and the analog single event transient (ASET),dominate the radiation response of an advanced integrated circuit. In this paper,we have reviewed the basic mechanisms of SEU and SET and discussed the predominant effects of advanced technology,such as MBU,multiple single event transients (MSETs),pulse broadening,and quenching. The influence of various factors on SEU and SET were also discussed. We also reviewed the mitigation of SEU and MBU in the memory circuit and that of SET in digital and analog circuits using circuit design techniques as well as layout design techniques.

With feature size scaling to 28 nm and even smaller,the reliability challenge brought by single event soft error has been becoming more severe. SET and SEU would remain the biggest contributor for soft error in future technology. New effects would also be observed due to the smaller feature size as well as new processes,such as FinFET. The mitigation technique of single event soft error would become more challenging,which calls for a combination of circuit hardening and layout hardening. Also,the need for custom designed mitigation techniques for different circuits would increase in future applications.