J. Semicond. > 2015, Volume 36 > Issue 3 > 034007
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SEMICONDUCTOR DEVICES

A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge accumulation effect

Ruichao Tian, Xiaorong Luo, Kun Zhou, Qing Xu, Jie Wei, Bo Zhang and Zhaoji Li

+ Author Affiliations

 Corresponding author: Xiaorong Luo, E-mail: xrluo@uestc.edu.cn

DOI: 10.1088/1674-4926/36/3/034007

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Abstract: A novel silicon-on-insulator (SOI) super-junction (SJ) LDMOS with an ultra-strong charge accumulation effect is proposed. It has two key features: an assisted-accumulation trench-type extending gate (TEG) with a high-k (HK) dielectric and a step-doped N pillar (TEG-SD SJ LDMOS). In the on-state, electrons accumulate at the sidewall of the HK dielectric from the source to the drain by the TEG. Furthermore, the high permittivity of the HK dielectric leads to an ultra-strong charge accumulation effect. As a result, an ultra-low resistance current path is formed. The specific on-resistance (Ron,sp) is thus greatly reduced and is independent of the drift doping concentration. In the off-state, the step-doped N pillar effectively suppresses the substrate-assisted depletion effect by charge compensation. Moreover, the reshape effect of the HK dielectric and the new electric field (E-field) peak introduced by the step-doped N pillar enhance the drift region E-field. Hence, the BV is improved. Simulation indicates that the TEG-SD SJ LDMOS achieves an extremely low Ron,sp of 1.06 mΩ · cm2 and a BV of 217 V. Compared with the conventional SJ LDMOS, the TEG-SD SJ LDMOS decreases the Ron,sp by 77.5% and increases the BV by 33%, exhibiting a high figure of merits (FOM = BV2/Ron,sp) of 44 MW/cm2.

Key words: charge accumulation effect, super junction, breakdown voltage, specific on-resistance



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Fig. 1.  (a) Three-dimensional (3D) schematic structure of the TEG-SD SJ LDMOS. (b) Cross section along the \textit{AA'} plane and schematic electron distribution. (c) Equivalent resistances and MIS capacitance in the on-state.

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Fig. 2.  Electron concentration distribution in on-state at $y=$ 0.01 $\mu $m by simulation ($V_{\rm GS}$ $=$ 15 V and $V_{\rm DS}$ $=$ 0.5 V). (a) TEG-SD SJ LDMOS at $k$ $=$ 200. (b) Con. SJ LDMOS.

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Fig. 3.  (a) Simulated current density along the $z$ direction ($V_{\rm GS}$ $=$ 15 V and $V_{\rm DS}$ $=$ 0.5 V, $x$ $=$ 8 $\mu $m, $y$ $=$ 1 $\mu $m, 0 $\leqslant$ $z$ $\leqslant$ 0.5 $\mu $m). (b) Output characteristics at $V_{\rm GS}$ $=$ 15 V.

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Fig. 4.  Equi-potential contours in simulation (7 V/contour) for (a) Con. SJ, BV $=$ 163 V ($N_{\rm D}$ $=$ 3.1 $\times$ 10$^{16}$ cm$^{-3})$, (b) TEG SJ, $k$ $=$ 200, BV $=$ 190 V ($N_{\rm D}$ $=$ 3.4 $\times$ 10$^{16}$ cm$^{-3})$, (c) TEG-SD SJ, $k$ $=$ 200, BV $=$ 217 V ($L_{\rm n}$ $=$ 1/2 $L_{\rm d}$, $\Delta N$ $=$ 2.6 $\times$ 10$^{16}$ cm$^{-3})$, and (d) surface E-field distribution ($y$ $=$ 0.01 $\mu $m, $z$ $=$ 0.3 $\mu $m).

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Fig. 5.  (a) BV versus $L_{\rm n}$ at $k$ $=$ 200 for the TEG-SD SJ LDMOS. (b) Dependences of BV and $R_{\rm on, sp}$ on $N_{\rm D}$, $k$ $=$ 200.

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Fig. 6.  Change imbalance factor $\eta$.

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Fig. 7.  Dependences of BV and $R_{\rm on, sp}$ on $k$ for the TEG-SD SJ LDMOS.

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Fig. 8.  Key process steps for fabricating the TEG-SD SJ LDMOS. (a) Etch trench, deposit the HK dielectric and CMP (chemical mechanical polishing). (b) Etch the HK dielectric, refill the trench with polysilicon and CMP. (c) Implant to form the P-well and the N$_{1}$ region, define the gate with oxide and polysilicon. (d) N$^{+}$ drain region implantation and form the diode D1. (e) P$^{+}$ regions and N$^{+}$ source implantation. (f) Passivation, etch vias and form electrodes.

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Table 1.   Device specifications.

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Table 2.   BV, $R_{\rm on, sp}$ and FOM $=$ BV$^{2}$/$R_{\rm on, sp}$ for TEG-SD SJ, TEG SJ and Con. SJ LDMOS.

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    Received: 05 August 2014 Revised: Online: Published: 01 March 2015

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      Article Navigation >  Journal of Semiconductors  > 2015  >  36(3): 034007
      Ruichao Tian, Xiaorong Luo, Kun Zhou, Qing Xu, Jie Wei, Bo Zhang, Zhaoji Li. A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge accumulation effect[J]. Journal of Semiconductors, 2015, 36(3): 034007. doi: 10.1088/1674-4926/36/3/034007 ****R C Tian, X R Luo, K Zhou, Q Xu, J Wei, B Zhang, Z J Li. A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge accumulation effect[J]. J. Semicond., 2015, 36(3): 034007. doi: 10.1088/1674-4926/36/3/034007.
      Citation:
      Ruichao Tian, Xiaorong Luo, Kun Zhou, Qing Xu, Jie Wei, Bo Zhang, Zhaoji Li. A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge accumulation effect[J]. Journal of Semiconductors, 2015, 36(3): 034007. doi: 10.1088/1674-4926/36/3/034007 ****
      R C Tian, X R Luo, K Zhou, Q Xu, J Wei, B Zhang, Z J Li. A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge accumulation effect[J]. J. Semicond., 2015, 36(3): 034007. doi: 10.1088/1674-4926/36/3/034007.
      shu

      A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge accumulation effect

      DOI: 10.1088/1674-4926/36/3/034007

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      Funds:

      Project supported by the National Natural Science Foundation of China (Nos. 61176069, 61376079) and the Program for New Century Excellent Talents in University of Ministry of Education of China (No. NCET-11-0062).

      More Information
      • Corresponding author: E-mail: xrluo@uestc.edu.cn
      • Received Date: 2014-08-05
      • Accepted Date: 2014-09-18
      • Published Date: 2015-01-25

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