J. Semicond. > 2015, Volume 36 > Issue 6 > 065004
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SEMICONDUCTOR INTEGRATED CIRCUITS

A high linearity X-band SOI CMOS digitally-controlled phase shifter

Liang Chen1, 2, , Xinyu Chen1, Youtao Zhang1, 3, Zhiqun Li2 and Lei Yang1

+ Author Affiliations

 Corresponding author: Liang Chen, Email: 289970852@qq.com

DOI: 10.1088/1674-4926/36/6/065004

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Abstract: This paper proposed an X-band 6-bit passive phase shifter (PS) designed in 0.18 μm silicon-on-insulator (SOI) CMOS technology, which solves the key problem of high integration degree, low power, and a small size T/R module. The switched-topology is employed to achieve broadband and flat phase shift. The ESD circuit and driver are also integrated in the PS. It covers the frequency band from 7.5 to 10.5 GHz with an EMS phase error less than 7.5°. The input and output VSWRs are less than 2 and the insertion loss (IL) is between 8-14 dB across the 7.5 to 10.5 GHz, with a maximum IL difference of 4 dB. The input 1 dB compression point (IP 1dB) is 20 dBm.

Key words: digitally-controlled phase shifter, CMOS technology, T/R module



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Fig. 1.  Cross section of (a) SOI CMOS NFET and (b) standard CMOS NFET.

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Fig. 2.  Performance comparison of SOI CMOS and standard CMOS switch.

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Fig. 3.  A switched-topology phase shifter.

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Fig. 4.  Schematic of a switch.

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Fig. 5.  Replace the single FET with $N$-staked FET.

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Fig. 6.  Parasitic parameters of SOI CMOS FET.

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Fig. 7.  (a) Comparison of the 2nd harmonics. (b) Comparison of the 3rd harmonics.

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Fig. 8.  The topology for 22.5$^\circ$ and 45$^\circ$ blocks. (a) Schematic of the phase shift block. (b) Equivalent circuit at reference state. (c) Equivalent circuit at phase shift state.

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Fig. 9.  Simulated relative phase shifts of 22.5$^\circ$ and 45$^\circ$.

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Fig. 10.  Schematic of a 5.625$^\circ$ phase shifter block.

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Fig. 11.  Schematic of an 11.25$^\circ$ phase shifter block.

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Fig. 12.  The simulated relative phase shifts of 5.625$^\circ$ and 11.25$^\circ$.

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Fig. 13.  Schematic of (a) 90$^\circ$ and (b) 180$^\circ$ phase shifter block.

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Fig. 14.  Simulated (a) phase shift and (b) IL specifics.

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Fig. 15.  ESD protection circuit of (a) control signal port and (b) power port.

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Fig. 16.  Schematic of the driver.

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Fig. 17.  Photograph of digital-controlled phase shifter.

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Fig. 18.  (a) Measured relative phase shifts for 64 states of the phase shifter. (b) EMS phase error. (c) Measured input VSWR. (d) Output VSWR. (e) Insertion loss for 64 states. (f) Input 1 dB compression point.

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Table 1.   Performance comparison of the phase shifter.

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    Received: 04 November 2014 Revised: Online: Published: 01 June 2015

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      Article Navigation >  Journal of Semiconductors  > 2015  >  36(6): 065004
      Liang Chen, Xinyu Chen, Youtao Zhang, Zhiqun Li, Lei Yang. A high linearity X-band SOI CMOS digitally-controlled phase shifter[J]. Journal of Semiconductors, 2015, 36(6): 065004. doi: 10.1088/1674-4926/36/6/065004 ****L Chen, X Y Chen, Y T Zhang, Z Q Li, L Yang. A high linearity X-band SOI CMOS digitally-controlled phase shifter[J]. J. Semicond., 2015, 36(6): 065004. doi: 10.1088/1674-4926/36/6/065004.
      Citation:
      Liang Chen, Xinyu Chen, Youtao Zhang, Zhiqun Li, Lei Yang. A high linearity X-band SOI CMOS digitally-controlled phase shifter[J]. Journal of Semiconductors, 2015, 36(6): 065004. doi: 10.1088/1674-4926/36/6/065004 ****
      L Chen, X Y Chen, Y T Zhang, Z Q Li, L Yang. A high linearity X-band SOI CMOS digitally-controlled phase shifter[J]. J. Semicond., 2015, 36(6): 065004. doi: 10.1088/1674-4926/36/6/065004.
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      A high linearity X-band SOI CMOS digitally-controlled phase shifter

      DOI: 10.1088/1674-4926/36/6/065004
      • 1.

        Nanjing Electronic Devices Institute, Guobo Electronics Co. Ltd, Nanjing 210016, China

      • 2.

        RF & OE IC Institute, Southeast University, Nanjing 210096, China

      • 3.

        Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing 210016, China

      More Information
      • Corresponding author: Email: 289970852@qq.com
      • Received Date: 2014-11-04
      • Accepted Date: 2014-12-29
      • Published Date: 2015-01-25

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