1. Introduction

With the rapid development of portable devices such as cellular phones and tablet computers, the boost DC-DC converter has gained great popularity in recent years, because of its wide application in the power management unit (PMU). High efficiency and large load capability have gained much importance in boost converters which lead to the trend of the use of large-sized rectified PMOS power transistors instead of the Schottky diode. However, it is very difficult to start up boost converters smoothly following this trend.

However, both inrush current and over-shoot voltage will shorten the lifespan of the battery in boost converters for the fact that the inductor current will keep rising during the start-up process until the output voltage exceeds the input. This situation deteriorates in the synchronous boost DC-DC converter for its output voltage start from zero while the asynchronous converter's output voltage start from input voltage. The higher the input voltage is, the larger the inrush current and correspondingly the easier the over-shoot of the output voltage are. Many start-up methods have been reported to address this problem^[1-10]. The scheme proposed in Reference [1] is to pull the gate of the PMOS down to ground so that the inductor current will increase slowly with the rise of output voltage until the output voltage is close to the input voltage and then switching begins. However, this method is only applicable in low input voltage. Some other solutions presented in References [2, 3] are not practical in real conditions which just slow down the ramp of the input voltage to suppress the inrush current. References [4, 5] present a constant current pre-charge circuit which can diminish the inrush current even at higher input voltage, but the converter may be stuck in the start-up operation when the boost DC-DC converter is heavy loaded and over-shoot may occur when the load is close to zero. The ramp-based solutions presented in References [6, 7] take a long time to complete the start-up process. There are also off-chip solutions to start up, such as Reference [8], which has an external pin connecting with an external capacitor to control the soft-start process. However, this solution needs an additional pin, and increases PCB area. Methods proposed in References [9, 10] are only applicable in a digital circuit.

In this paper, a load adaptive start-up circuit is proposed which can always keep the inductor current enough to start up the converter even at heavy load while inrush current and over-shoot voltage will not appear at a light load with high input voltage. During the start-up, if a short circuit or an over temperature occurs, the inductor current will keep at a low value to protect the chip.

2. Conventional start-up technique

A conventional start-up scheme which has an external pin connecting with an external capacitor (C_t) charged by a constant current (I_biast) can be found in most boost converters, such as References [8-11], illustrated in Figure 1. The C_t and I_biast are proposed to control the soft-start process which can be described as the output of EA rises linearly with the rising of V_ct until V_ct exceeds the reference voltage, then the start-up phase is over and the converter begins to regulate the loop normally.

However, there is an inevitable compromise between the start-up time and inrush current. The start-up time is dependent on the value of the C_t and I_bias. Reference [11] suppresses the inrush current but with a long start-up time, while Reference [12] shortens the start-up time, and the inrush current is large. It is impossible to start up the converter successfully at heavy load if the start-up time is too long. As previously mentioned, this method will increase PCB area. Although another method of replacing C_t with the external compensation capacitors to reduce external pin and PCB area has been presented in Reference [13], it is hard to find a proper capacitance to satisfy start-up and stability simultaneously.

3. Principle of proposed start-up technique

The architecture of a current mode synchronous boost DC-DC converter with the proposed start-up scheme, which is in a dashed rectangle, is presented in Figure 2. This start-up scheme is divided into three stages, called pre-charge phase, ring oscillator operation phase, and system loop start-up phase. Normally, the supply voltage of the driver for the MN and MP power transistors is provided by the output voltage (V_out) because the input voltage (V_in) cannot totally shut off the MP power transistors. However, when the converter is enabled, the V_out voltage is too low to power the driver. So the pre-charge phase is introduced to charge up V_out close to V_in through the MP slowly. In addition, the inrush current will be too large when the MN is turned on before V_out is equal to V_in. The ring oscillator operation phase guarantees the converter operates normally when V_in < 2.3 V to widen the range of input voltage and improve the load adaptive. The system loop start-up phase provides a smooth switch between the pre-phase and the system loop start-up phase to minimize current drawn from the input voltage and avoid inrush current and over-shoot voltage.

Table 1 presents three phases during the proposed start-up process. As output voltage increase, the converter enters into the next phase.

3.1 The operation of pre-charge phase

In the pre-charge phase, the output voltage is charged from zero to the input voltage through the PMOS power transistors. When the chip is powered on and enabled, the block UVLO (under voltage lock) and bandgap will operate. If the V_in is under 1.4 V, the power transistors are turned off and the body of the PMOS power transistors is forced to link V_in, so no current will flow to the output. Once V_in is over 1.4 V, the boost converter will come into the normal start-up process. The structure of the boost converter in pre-charge phase is shown in Figure 3.

The MP and MS operate as current mirrors so that a limited current will flow into the V_out and inrush current will not occur in this phase. The mirrored current is roughly shown as:

$\begin{equation} \label{eq1} I_{\rm MP} \approx N \frac{V_{\rm ref}}{R_{\rm set} }. \end{equation}$

(1)

The channel-length modulation effect will make this equation inaccurate but the error is acceptable. The transistor MN1 aims at decreasing the voltage difference across the MP and MS thus diminishing the channel-length modulation effect. There is a problem that an initial limited low current will make the chip stuck in the pre-charge phase under heavy load while large current will result in over-shoot voltage under light load. The proposed technique is a step-increasing pre-charge current by increasing the V_ref and decreasing R_set gradually to promote the inductor current. Switch S1 to S6 turned on or off is determined by the counter decoder. In order to determine the on time of each switch, we assume pre-charge current is constant and the time for the converter to exit the pre-charge phase can be expressed as:

$\begin{equation} \label{eq2} T_{\text{ pre-charge}} =\frac{C_{\rm out} V_{\rm in}}{I_{\text{ pre-charge}} -I_{\rm load} }. \end{equation}$

(2)

C_out is the output capacitor and I_pre-charge denotes the pre-charge current. The pre-charge time is proportional to the V_in and I_load, and Table 2 shows calculation results of the pre-charge time in the extreme conditions.

According to the above table, the on time for switch T_S1 is set to be 500 μs and T_SN (N = 2, 3, 4, 5, 6) is 300 μs. Switches are turned on one-by-one and the pre-charge current will gradually increase so that the pre-charge current is slightly greater than the load current after the converter exits this phase. The pre-charge current when switches SN (N = 1, 2, 3, 4, 5, 6) are on is shown in Figure 3. The pre-charge time is dependent on the load and the heavier the load, the longer the pre-charge time. The minimum time for the pre-charge phase is about 200 μs at V_in = 1.4 V and I_load = 0 A while the longest time is over 2 ms at V_in = 4.2 V and I_o = 2.1 A in the normal operation.

The chip exits the pre-charge phase when V_out is equal to V_in - 150 mV and Mn2 will turn off to decrease the quiescent current. However, if a fault mode occurs, the chip will stay in pre-charge phase and the current is limited to protect the chip. The situations and corresponding operations which may occur in the pre-charge phase are shown in Table 3.

The operational amplifier (OP) in Figure 3 is also very critical which decides whether the pre-charge phase can operate as expected or not. The schematic of the OP is shown in Figure 4. The supply voltage of the output stage is V_b, which is the body voltage of the PMOS power transistors. When the boost converter exits the pre-charge phase, the chip begins switching. The driver of the power transistor is powered by V_out, and V_b will also connect to the V_out, so that no current will flow through the body of the transistor M7.

3.2 The ring oscillator phase

This phase is optional. When the input voltage is higher than 2.3 V, this phase will be skipped. Otherwise, the chip will go through this phase. Most of the circuits are powered by V_out, but it is too low to supply some critical circuits such as error amplifier (EA) and current sense circuit when V_out is close to V_in. In this phase, the converter begins switching at a fixed 50% duty cycle which is produced by a ring oscillator. When the output voltage rises from V_in to 2.3 V, the converter will exit this phase. To boost the output voltage from 1.4 to 2.3 V, the minimum duty (Dmin) can be expressed as:

$\begin{equation} \label{eq3} D_{\rm min } =1-\frac{V_{\rm in}}{V_{\rm out}}\bigg| _{V_{\rm in}=1.4 \text{ V}, V_{\rm out}=2.3 \text{ V}}=40\% . \end{equation}$

(3)

From Equation (3), the fixed 50% duty cycle is enough to boost the V_out to 2.3 V and by switching at a fixed 50% duty cycle. An inherent current limit is set by the rate of rise of the inductor current and rate of discharge of the inductor current.

3.3 The system loop soft-start phase

In this phase, the system loop is ready to operate normally. Figure 5 shows the schematic of the proposed EA with soft-start function and Figure 6 is the schematic of current limit circuit.

V_out is expected to rise slowly following the V_cp. When the system enters into this phase, V_out is close to V_in or 2.3 V and FB is at a certain voltage. As a result, the V_cp is expected to track FB, otherwise the output of the EA, Comp, will keep low; at first V_cp is lower than FB thus resulting in a drop of inductor current. A simple schematic is used to avoid this situation as shown in Figure 5. Before the converter enters into this phase, Ctrl is high, MN1 is on, MP2 is off and Cp records the FB. Once the converter enters into this phase, the Ctrl is low and FB will follow the V_cp which slowly rises by charging the capacitor Cp through I_baisp. In addition, when V_cp rises above V_ref, the V_ref will substitute V_cp to regulate the output voltage.

At the same time, a current limit function is activated to limit the inductor current. During the soft-start time, the current limit is gradually rising while the initial value is adjusted according to the load current. Compared with the constant current limit, the adjustable initial current limit avoids the drop of the output voltage at heavy load and the over-shoot of the output voltage at light load. The proposed technique is implemented by common use of the digital logic signal SN (N = 1, 2, 3, 4, 5, 6) in the pre-charge phase. For example, when the converter exits from pre-charge phase, and the switch S3 is on, the initial current limit will set at 1.6 A and gradually increases. The state of the switch indicates the load situation. We can obtain the value of current limit by:

$\begin{equation} \label{eq4} I_{{\rm CL}N} =\frac{V_{\rm out} I_{{\rm MP}N} }{V_{\rm in}} \eta, \end{equation}$

(4)

where I_CLN (N = 1, 2, 3, 4, 5, 6) is the value of current limit, I_MPN is the value of step-increasing constant inductor current during pre-charge phase, and η is the efficiency of the boost converter. Set V_in = 2.3 V, V_out = 5 V, η = 90%, and we can get I_CLN ≈ 1.95I_MPN.

When the S6 is on, the current limit is 4.5 A, the maximum value which we expect for the converter to regulate normally. Finally, the output voltage expects to reach the set point while the inrush inductor current is suppressed with the current limit circuit.

4. Simulation results

The synchronous boost DC-DC converter with the proposed start-up scheme is based on TSMC 0.35 μm CMOS process and the simulation and verification of the designed circuit by specter simulator is demonstrated as follows. Figure 7 shows the start-up process of the converter at V_in = 1.4 V, I_load = 100 mA (R_load = 50 Ω) and V_out = 5 V.

The simulation result shows the V_out successfully start up at V_in = 1.4 V, and the start-up process has three phases. In order to charge up the output voltage to 5 V from 2.3 V, the input current must reach 2 A during system loop soft-start phase. From the simulation results, we can learn that the input current steps up slowly from 1 to 2 A instead of an inrush current 2 A. The start-up process is smooth without inrush current and over-shoot voltage.

Figure 8(a) and Figure 8(b) are the simulation waveform of the circuit at V_in = 3.6 V, I_load = 2.1 A (R_load = 2.4 Ω) and I_o = 0 A, respectively.

The start-up time is largely dependent on the load. When the load is zero, the total start-up time is less than 450 μs while it is more than 2 ms at heavy load of 2.1 A. There are only two phases at V_in = 3.6 V and both the output voltage and inductor current rise slowly and steadily.

Simulation of the short protection of V_out of the converter is presented in Figure 9. Before 2.5 ms, the converter operates normally. The output voltage is 5 V and the I_load = 1 A (R_load = 5 Ω). Suddenly, when the output shorts to the ground, the converter will come back to the start-up process. At first, the inductor current will increase and then is limited to the minimum value of 259 mA to decrease the power loss of the converter. The converter will keep this state until the short circuit situation is removed.

5. Conclusion

The performances of the boost converter integrated proposed start-up method are summarized in Table 4 and compared with the other designs with different start-up technology.

In this paper, a load adaptive start-up scheme for synchronous boost DC-DC converter is studied. The start-up process is divided into three phases. In addition, the inductor current traces the load current and is limited in all the phases to suppress the inrush current and prevent over-shoot voltage. The converter can start up as low as 1.4 V and output current can be as large as 2.1 A. Moreover, the total soft-start time is dependent on the load situation and heavy load will prolong the soft-start time which make it an excellent candidate for battery powered devices for it gives them a steady power supply without inrush current and over-shoot voltage.