Fig. 1.
Architecture for baseline router.
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| Citation: |
Xiaofeng Zhou, Lu Liu, Zhangming Zhu, Duan Zhou. A low overhead load balancing router for network-on-chip[J]. Journal of Semiconductors, 2016, 37(11): 115003. doi: 10.1088/1674-4926/37/11/115003
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X F Zhou, L Liu, Z M Zhu, D Zhou. A low overhead load balancing router for network-on-chip[J]. J. Semicond., 2016, 37(11): 115003. doi: 10.1088/1674-4926/37/11/115003.
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A low overhead load balancing router for network-on-chip
DOI: 10.1088/1674-4926/37/11/115003
More Information
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Abstract
The design of a router in a network-on-chip (NoC) system has an important impact on some performance criteria. In this paper, we propose a low overhead load balancing router (LOLBR) for 2D mesh NoC to enhance routing performance criteria with low hardware overhead. The proposed LOLBR employs a balance toggle identifier to control the initial routing direction of X or Y for flit injection. The simplified demultiplexers and multiplexers are used to handle output ports allocation and contention, which provide a guarantee of deadlock avoidance. Simulation results show that the proposed LOLBR yields an improvement of routing performance over the reported routing schemes in average packet latency by 26.5%. The layout area and power consumption of the network compared with the reported routing schemes are 15.3% and 11.6% less respectively.-
Keywords:
- NoC,
- low overhead,
- load balancing,
- router
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References
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