J. Semicond. > 2016, Volume 37 > Issue 2 > 024003
|

SEMICONDUCTOR DEVICES

Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET

Sangeeta Singh, P. N. Kondekar and Pawan Pal

+ Author Affiliations

 Corresponding author: Sangeeta Singh, Email: sangeeta.singh@iiitdmj.ac.in

DOI: 10.1088/1674-4926/37/2/024003

PDF

Abstract: We investigate the transient behavior of an n-type double gate negative capacitance junctionless tunnel field effect transistor (NC-JLTFET). The structure is realized by using the work-function engineering of metal electrodes over a heavily doped n+ silicon channel and a ferroelectric gate stack to get negative capacitance behavior. The positive feedback in the electric dipoles of ferroelectric materials results in applied gate bias boosting. Various device transient parameters viz. transconductance, output resistance, output conductance, intrinsic gain, intrinsic gate delay, transconductance generation factor and unity gain frequency are analyzed using ac analysis of the device. To study the impact of the work-function variation of control and source gate on device performance, sensitivity analysis of the device has been carried out by varying these parameters. Simulation study reveals that it preserves inherent advantages of charge-plasma junctionless structure and exhibits improved transient behavior as well.

Key words: negative capacitance, intrinsic gain, transconductance generation factor, intrinsic bias boosting



[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
Fig. 1.  Schematic cross-sectional view of (a) JLTFET and (b) NC-JLTFET.

DownLoad: Full-Size Img PowerPoint
Fig. 2.  Qualitative comparison of the transfer characteristics for NC-JLTFET and JLTFET at different operating bias, $V_{\rm DS}$.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  (a) Transconductance $(g_{\rm m})$ of NC-JLTFET and JLTFET at different operating bias $V_{\rm DS}$, (b) output resistance ($R_{\rm o}$) and output conductance ($g_{\rm o}$) for NC-JLTFET at $V_{\rm DS}$ $=$ 1 V, (c) intrinsic gain $(g_{\rm m}R_{\rm o})$ of NC-JLTFET and JLTFET for $V_{\rm DS}$ $=$ 1 V.

DownLoad: Full-Size Img PowerPoint
Fig. 4.  Transconductance generation factor ($g_{\rm m}/I_{\rm D}$) of the NC-JLTFET as a function of $V_{\rm GS}$ at $V_{\rm DS}$ $=$ 0.4 and 1 V.

DownLoad: Full-Size Img PowerPoint
Fig. 5.  Intrinsic gate delay and unity gain bandwidth ($f_{\rm T}$) of the NC-JLTFET as a function of $V_{\rm GS}$ at $V_{\rm DS}$ $=$ 1 V.

DownLoad: Full-Size Img PowerPoint
Fig. 6.  (Color online) Effect of control gate work-function variation on the transfer characteristics ($I_{\rm D}$--$V_{\rm GS}$) of NC-JLTEFT with $L_{\rm G}$ $=$ 20~nm, $t_{\rm Si}$ $=$ 5 nm, $t_{\rm ox}$ $=$ 2 nm.

DownLoad: Full-Size Img PowerPoint
Fig. 7.  Demonstration of point SS, $I_{\rm ON}/I_{\rm OFF}$, threshold voltage ($V_{\rm TH}$) and DIBL variation as a function of control gate work-function with $L_{\rm G}$ $=$ 20 nm, $t_{\rm Si}$ $=$ 5 nm, $t_{\rm ox}$ $=$ 2 nm.

DownLoad: Full-Size Img PowerPoint
Fig. 8.  (Color online) $I_{\rm D}$ versus the $V_{\rm GS}$ curve of the NC-JLTEFT with TiO$_{2}$ and PZT gate stack for fixed source gate work-function variation at $V_{\rm DS}$ $=$ 1 V.

DownLoad: Full-Size Img PowerPoint
Fig. 9.  Comparison of point SS, $I_{\rm ON}/I_{\rm OFF}$ ratio, threshold voltage $V_{\rm TH}$ and DIBL for fixed source gate work-function ($\phi_{\rm S}$) variation for NC-JLTFET with $L_{\rm G}$ $=$ 20 nm, $t_{\rm Si}$ $=$ 5 nm, $t_{\rm ox}$ $=$ 2 nm at $V_{\rm DS}$ $=$ 1 V.

DownLoad: Full-Size Img PowerPoint

Table 1.   Simulation parameters for conventional JL-TFET and NCJLTFET.

DownLoad: CSV
DownLoad: CSV
DownLoad: CSV
DownLoad: CSV
DownLoad: CSV
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]

    • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 3172 Times PDF downloads: 31 Times Cited by: 0 Times

    History

    Received: 12 June 2015 Revised: Online: Published: 01 February 2016

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Send
      Article Navigation >  Journal of Semiconductors  > 2016  >  37(2): 024003
      Sangeeta Singh, P. N. Kondekar, Pawan Pal. Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET[J]. Journal of Semiconductors, 2016, 37(2): 024003. doi: 10.1088/1674-4926/37/2/024003 ****S Singh, P. N. Kondekar, P Pal. Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET[J]. J. Semicond., 2016, 37(2): 024003. doi: 10.1088/1674-4926/37/2/024003.
      Citation:
      Sangeeta Singh, P. N. Kondekar, Pawan Pal. Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET[J]. Journal of Semiconductors, 2016, 37(2): 024003. doi: 10.1088/1674-4926/37/2/024003 ****
      S Singh, P. N. Kondekar, P Pal. Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET[J]. J. Semicond., 2016, 37(2): 024003. doi: 10.1088/1674-4926/37/2/024003.
      shu

      Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET

      DOI: 10.1088/1674-4926/37/2/024003
      More Information
      • Corresponding author: Email: sangeeta.singh@iiitdmj.ac.in
      • Received Date: 2015-06-12
      • Published Date: 2016-01-25

      Catalog

        Journal of Semiconductors © 2017 All Rights Reserved   京ICP备05085259号-2

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return