1. Introduction

Silicon carbide (SiC),which exhibits a wider band gap as well as a superior breakdown field and thermal conductivity over conventional Si,has gained considerable attention for a new generation of power devices^{[1, 2, 3]}. However,the metal oxide semiconductor field effect transistors (MOSFETs) fabricated on 4H-SiC present low inversion channel mobility and have a gate oxide reliability problem due to the high density of interface traps at the SiO$_{2}$/SiC interface^{[4, 5, 6]}. The nitridation process that nitrogen is incorporated into the SiO$_{2}$/SiC interface,is considered to play a major role in defect passivation^{[6, 7, 8]}. More recently,new routes to improve channel performance have also been proposed,including alkali and alkaline earth elements passivation^[9]. Although other processes such as wet oxidation^[10],sodium-contaminated oxidation^{[11, 12]},or POCl$_{3}$ annealing^{[13, 14]} also improve the mobility,nitridation is the most common process,taking reliability and stability into consideration. It lowers the $D_{\rm IT}$ and increases the field effect mobility from 5 to 30 cm$^{2}$/(V$\cdot$s),which makes the commercialization of SiC MOSFETs a reality. However,the peak electron inversion-layer mobility at moderate doping levels is expected to be 200 cm$^{2}$/(V$\cdot$s) or higher,considering the SiC bulk electron mobility of 954 cm$^{2}$/(V$\cdot$s)^{[15, 16]} }$. As the development of the characterization technique,the problems of the nitridation process are gradually revealed. Large frequency dispersion is observed by low-temperature$C$-$V$ measurements^[17]. It is indicated that very fast states still exist at the SiO$_{2}$/SiC interface even after NO annealing. The traditional high-low method with a maximum frequency of 1 MHz will seriously underestimate the $D_{\rm IT}$^[18]. These conclusions are further confirmed by Kimoto's group,and they find that only a part of the fast states can be detected by conductance measurements up to 100 MHz at room temperature^[19]. They also propose a $C$-$\psi_{\rm S}$ method to accurately evaluate the $D_{\rm IT}$ at the SiO$_{2}$/SiC interface^[20]. Recently,a low temperature conductance method,which is supposed to be more suitable for characterization of very fast interface states at the nitrided interface,has been used to study the effects of the fast interface states^[21]. Yoshioka reports that the capture cross section of these fast states is uniquely larger than that of conventional interface states and the density of these fast states also increases with NO temperature.

Carbon related defects have been found at the SiO$_{2}$/SiC interface^{[8, 22, 23]}. Physical defects that are attributed to the high $D_{\rm IT}$ are carbon clusters,C dangling bonds and a nonstoichiometric sub-oxide near the interface^{[24, 25, 26]}. It is suggested that NO annealing can dissolve interfacial carbon clusters,which leads to a reduction of the size of these clusters and possibly generates carbon dangling bonds at the interface^{[8, 27, 28]}. In addition,since the nitridation process is usually performed at a temperature as high as 1350 $\du$,sub-oxide generation may become non-negligible during the high temperature process^{[29, 30]}. Hydrogen passivation treatment (forming gas annealing: FGA) is routinely applied for Si-based MOS devices. Theoretical studies show that H$_{2}$ can passivate isolated C dangling bonds as well as Si related defects^[31]. It has been shown that nitrogen plasma exposure promotes hydrogen passivation of electrical defects at the SiO$_{2}$/SiC interface^[32].

In this article,we propose a treatment that combines NO annealing and FGA treatment to improve the electrical properties of the SiO$_{2}$/SiC interface further. The role of nitrogen and hydrogen passivation on the SiO$_{2}$/4H-SiC interface is evaluated by low-temperature conductance measurements.

2. Experiment

MOS capacitors were used to characterize the effects of the passivation treatments on the interface of SiO$_{2}$/SiC. Figure 1 represents the structure of the SiC MOS capacitor and its fabrication process flow. The starting substrate was an n-type 4H-SiC (0001) wafer with a 12 $\mu$m epilayer ($N_{\rm D}$ $\approx$ 4.4 $\times$ 10$^{15}$ cm$^{-3})$. After standard RCA cleaning,45-nm-thick oxides were formed by dry oxidation at 1300 $\du$,followed by post-oxidation annealing at 1300 $\du$ in N$_{2}$. Film thickness was determined by UVISEL spectroscopic ellipsometry^[33]. Nitridation was carried out in NO (sample label: NO) at 1300 $\du$ for 120 min. During the nitridation,an extra oxide growth took place and the thickness of SiO$_{2}$ was about 61 nm. FGA annealing was performed in forming gas (5% H$_{2}$ $+$ 95% N$_{2})$ ambient (sample label: FGA). For the combined treatment (sample label: NO & FGA),the NO & FGA sample first underwent nitridation and was then annealed in forming gas. A control sample without NO annealing or FG annealing was also prepared (sample label: as-oxidized). Circular Al electrodes (gate) with a diameter of 200 $\mu$m were deposited on the sample surface by a lift-off process.

The room temperature conductance measurements were measured at probe frequencies from 1 kHz to 1 MHz using a precision impedance analyzer (4284A,Agilent Technologies). For the NO sample and the NO & FGA sample,low temperature conductance measurements were also carried out at temperatures ranging from 150 to 293 K with a step of 30 K to characterize the fast states. Figure 2 shows the typical parallel-model capacitance ($C_{\rm P})$ and conductance ($G_{\rm P})$ for the MOS capacitors.

Based on an equivalent circuit shown in Figure 3,the interface state conductance ($G_{\rm PIT})$ was extracted from the measured impedance. Before applying the conductance method,the values of the $Z(\omega)$ were determined for each frequency from the impedance and $C_{\rm ox}$ measured in a strong accumulation region. Then,series resistance was removed from the measured impedance^[34]. The interface state density is linked to $G_{\rm PIT}$ by^[35]

where $\omega$ is the angular frequency,$S$ is the area of the gate electrode,and $e$ (1.602 $\times$ 10$^{-19}$ C) is the elementary electric charge. The interface state density ($D_{\rm IT})$,the time constant of the interface states ($\tau$),and the standard deviation ($\sigma )$ are determined using a simple method provided by Nicollian and Brews^[35]. The energy level ($E_{\rm c}$ - $E_{\rm T})$ of interface states is calculated from

by taking into account the Fermi level of the SiC epilayer ($E_{\rm c}$ - 0.24 eV) at room temperature. Here $\psi_{\rm s}$ is the surface potential determined from a comparison of an ideal $C$-$V$ curve and the measured high frequency $C$-$V$ curve. For the low temperature measurements,the incomplete dopant ionization effect in 4H-SiC is also taken into consideration when calculating the Fermi level^[36]. The stability of the flatband voltage was also evaluated by $C$-$V$ measurements.

3. Results and discussion

The $C$-$V$ characteristics measured with various frequencies from 1 kHz to 1 MHz for the MOS capacitors are shown in Figure 4. Both the as-deposited sample and the FGA sample show large frequency dispersion,which indicates the formation of an interface with a high density of interface defects. As for the NO sample and the NO & FGA sample,the $C$-$V$ curves agree well with each other. Figure 5 shows interface-state conductances ($G_{\rm PIT})$ at different gate voltages for these samples. A broad single peak is observed for the as-oxidized sample and FGA sample,which is consistent with $C$-$V$ results. From the peaks,$D_{\rm IT}$ values of the as-oxidized sample and FGA sample are determined at each gate voltage and shown in Figure 6(a) as a function of the energy level with reference to the conduction band edge of SiC. H$_{2}$ has only a limited effect on the $D_{\rm IT}$,which is accorded with earlier reports^[37]. Two reasons may account for this result. Firstly,H$_{2}$ can passivate Si dangling bonds and isolated C dangling bonds,but these kinds of defects are not the dominant defects in the as-oxidized SiO$_{2}$/SiC interface. Secondly,H$_{2}$ has a large diffusion barrier ($>$ 2.5 eV) in SiO$_{2}$ and needs a relatively high annealing temperature^[38]. Although FGA treatment has a small effect on the $D_{\rm IT}$,the values of time constant ($\tau )$ show a significant decrease compared with the as-oxidized sample,especially at a trap energy level close to the conduction band edge of SiC.

As shown in Figure 5,the NO sample and NO & FGA sample do not show any peaks throughout the measurable frequency range because these peaks take a maximum frequency higher than 1 MHz. However,it does not mean that there is a low density of interface states in these samples. It has been reported that the density of conventional states existing at an as-oxidized interface decreases significantly after NO annealing and new defects with a very fast time constant are observed^[19]. These fast interface states can respond to frequencies higher than 100 MHz at room temperature (RT),so it needs an ultra-high frequency measurement or other measurement approach. Since the response frequency of fast states is lowered with decreasing temperature,the $D_{\rm IT}$ is evaluated by low temperature conductance measurements for the NO sample and NO & FGA sample.

Here the impedance-frequency characteristics are measured in a temperature range of $T=$ 150 - 298 K and the peaks of $G_{\rm PIT}$ are only found in a range of $T$ $\le$ 210 K. Figure 7 shows the parallel-mode capacitance measured at low temperatures (210 K/180 K/150 K) for the NO & FGA sample. The frequency dispersion increases obviously with reducing the measurement temperature. Since the response frequency of interface states is lowered with decreasing temperature,for $T$ < 210 K,1 MHz is almost high enough for the $G_{\rm PIT}$ peak to be clearly observed. Figure 8 shows the $G_{\rm PIT}$ at different gate voltages for the NO & FGA sample. Distinct peaks are observed for both the samples. The $D_{\rm IT}$ of all the samples is then summarized in Figure 9. The detectable energy level is as shallow as 0.1 eV by low temperature measurements. Even though the $D_{\rm IT}$ decreases obviously after NO annealing,the interface states density is still more than 10$^{12}$ cm$^{-2}$ eV$^{-1}$ at shallower than 0.2 eV. The values of $D_{\rm IT}$ are reasonable compared with earlier reports^[21]. As for the NO & FGA sample,the $D_{\rm IT}$ is further reduced after additional FG annealing. Though FG annealing has a limited effect on the shallow traps,deeper in the energy bandgap ($E_{\rm C}$ - $E_{\rm T}$ $\ge$ 0.4 eV),the $D_{\rm IT}$ is reduced to less than 10$^{11}$ cm$^{-2}$ eV$^{-1}$.

As shown in Figure 9,FGA treatment at 450 $\du$ alone does not have any impact improvement of the electrical properties. It is well known that Si-O-C bonds and C-C clusters,as well as C dangling bonds are supposed to be the possible origins of interface states in SiC-MOS devices. However,the Nitridation process can dissolve carbon clusters and associated complex Si-O-C bonds,which leads to the formation of simple Si and C dangling bonds that can be readily terminated by H$_{2}$. Thus,the density of interface states ($E_{\rm C}$ - $E_{\rm T}$ $\ge$ 0.2 eV) decreases dramatically after a treatment combining NO and forming gas annealing. This result is consistent with the theoretical study that carbon-related defects can explain most of the observed interface states but not the high density near the conduction band of 4H-SiC^[39]. Figure 10 shows the interface-state conductance against temperature for the NO & FGA sample measured at 100 kHz. Multiple lines show the results measured at different gate voltages. The conventional interface-state conductance peak,which usually exists at the as-oxidized SiO$_{2}$/SiC interface and responds at room temperature,is effectively suppressed. The fast interface-state conductance peak is larger than the conventional interface-state conductance peak and is located at lower temperature in T-sweep measurements at 100 kHz. As for these fast interface states,we can rule out the possibility that simple Si dangling bonds and C dangling bonds,which were easy to be terminated with H$_{2}$,are the dominant component of these traps. Yoshioka reports that the density of fast states increases almost in proportion to the N concentration at the SiO$_{2}$/SiC interface^[21]. Distinct N peaks are also found for both the NO sample and the NO & FGA sample in XPS measurements as shown in Figure 11. N atoms accumulated at the interface by the process are considered as a possible origin of these shallow traps ($E_{\rm C}$ - $E_{\rm T}$ $\le$ 0.2 eV).

The stability of $V_{\rm FB}$ against the accumulation voltage is investigated at room temperature. All the $C$-$V$ sweeps (1 MHz) are started from -5 V,and the maximum accumulation voltage ($V_{\rm acc})$ is varied from 10 to 24 V with a 2-V step. The flatband voltage shifts corresponding to these $C$-$V$ curves are summarized in Figure 12. Significant positive $V_{\rm FB}$ shifts are observed for the as-deposited sample and FGA sample. Positive shifts occur when the acceptor-like deep interface states are filled with electrons under a strong accumulation region. Most of them are difficult to detrap and act like negative fixed charges. Thus,a positive shift of the $C$-$V$ curves is observed. The $V_{\rm FB}$ shift almost disappears for the NO & FGA sample. This is because the $D_{\rm IT}$ of the NO & FGA sample decreases by over an order of magnitude compared to that of the as-oxidized sample and especially at the deep energy level. It is indicated that the combined treatment of NO annealing and forming gas annealing is quite effective to suppress the $V_{\rm FB}$ shift for the SiC-MOS devices.

4. Conclusions

We investigate the role of nitrogen and hydrogen incorporation into the SiO$_{2}$/SiC interface by conductance measurements. Even though the $D_{\rm IT}$ is significantly reduced in the entire energy range after NO annealing,very fast states are observed at the nitride SiO$_{2}$/SiC interface and respond to frequencies higher than 1 MHz at room temperature. Through low-temperature conductance measurements,the conductance peak of the NO-annealed capacitor is clearly observed. Forming gas annealing alone is not effective for reducing interface defects,but hydrogen can terminate the residual Si and C dangling bonds generated after NO annealing and the $D_{\rm IT}$ is further reduced. The combined treatment of NO and forming gas annealing reduces the density of interface states in the deep energy trap level to less than 10$^{11}$ cm$^{-2}$ eV$^{-1}$. The stability of $V_{\rm FB}$ is also remarkably improved due to the reduction of $D_{\rm IT}$. It is indicated that combined treatment using the nitridation process in conjunction with hydrogen passivation is a promising method for improving the performance of SiC-based MOS devices.