Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO<sub>2</sub>/high-<i>k</i> gate stacked dielectric

S. Intekhab Amin; R. K. Sarin

doi:10.1088/1674-4926/37/3/034001

J. Semicond. > 2016, Volume 37 > Issue 3 > 034001

SEMICONDUCTOR DEVICES

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO₂/high-k gate stacked dielectric

S. Intekhab Amin and R. K. Sarin

+ Author Affiliations

Corresponding author: S. Intekhab Amin, Email: intekhabamin@gmail.com

DOI: 10.1088/1674-4926/37/3/034001

Abstract: A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.

Key words: junctionless transistor, direct tunneling gate current model, high-k gate stacked dielectric

References

[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]

Fig. 1. Schematic view of device structure of n-type DGJLT with gate oxide of SiO$_{2}$ and gate stack (SiO$_{2}$ $+$ high-$k)$ architecture. Gate oxide thickness,silicon body thickness and gate length are $t_{\rm ox}$,$t_{\rm si}$ and $L$ respectively.

DownLoad: Full-Size Img PowerPoint

Fig. 2. Surface potential model^[14] along the channel position for DGJLT at $V_{\rm GS}$ $=$ 0 V,$V_{\rm DS}$ $=$ 0 and 0.2 V.

DownLoad: Full-Size Img PowerPoint

Fig. 3. Comparison between direct gate tunneling model and numerical simulation for DGJLT with 2.0 nm EOT of SiO$_{2}$ at $V_{\rm DS}$ $=$ 1.0 V,where silicon film thickness $t_{\rm si}$ $=$ 10 nm,$\phi_{\rm m}$ $=$ 5.2 eV,$m_{\rm ox}$ $=$ 0.5$m_{0}$,band offset of 3.1 eV,and electron affinity of SiO$_{2}$ is 0.95 eV.

DownLoad: Full-Size Img PowerPoint

Fig. 4. Calibration of gate tunneling model with reported work^[10].

DownLoad: Full-Size Img PowerPoint

Fig. 5. Gate tunneling current density as a function of gate voltage with the variation of band offset values for EOT of SiO$_{2}$ is 1.5 nm at $V_{\rm DS}$ $=$ 1.0 V.

DownLoad: Full-Size Img PowerPoint

Fig. 6. Gate current density versus gate voltage of DGJLT with various gate to channel workfunction differences (flatband voltage,$\phi_{\rm MS})$.

DownLoad: Full-Size Img PowerPoint

Fig. 7. Conduction band offset with respect to $k$-values of dielectric material.

DownLoad: Full-Size Img PowerPoint

Fig. 8. Gate current density as a function of gate voltage of DGJLT for SiO$_{2}$ gate oxide of 1.5 nm,2.0 nm and gate stacked architecture of EOT $=$ 2.0 nm for Si$_{3}$N$_{4}$ and HfO$_{2}$ high-$k$ dielectric material at $V_{\rm DS}$ $=$ 1.0 V.

DownLoad: Full-Size Img PowerPoint

Fig. 9. Gate current density versus $k$-values of dielectric on a gate stacked architecture of DGJLT for a fixed EOT $=$ 2.0 nm by adjusting barrier height according to their respective $k$-values at $V_{\rm GS}$ $=$ 1.0 V and $V_{\rm DS}$ $=$ 1.0 V.

DownLoad: Full-Size Img PowerPoint

DownLoad: CSV

[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]

Search

GET CITATION

shu

Export: BibTex EndNote

Article Metrics

Article views: 2967 Times PDF downloads: 24 Times Cited by: 0 Times

History

Received: 05 July 2015 Revised: Online: Published: 01 March 2016

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO₂/high-k gate stacked dielectric

References

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO₂/high-k gate stacked dielectric

DOI: 10.1088/1674-4926/37/3/034001

Abstract

References

Proportional views

Catalog

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

References

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

DOI: 10.1088/1674-4926/37/3/034001

Abstract

References

Proportional views

Catalog

Export File

Citation

Format

Content

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO₂/high-k gate stacked dielectric

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO₂/high-k gate stacked dielectric