1. Introduction

As CMOS technologies advance, low-power electronic applications like portable devices develop rapidly. Such devices usually demand high power efficiency and small area in order to operate longer and integrate more easily, requiring higher-performance ADCs. Pipeline ADCs have been widely used, but require several op-amps and numerous comparators, which results in large power dissipation^[1]. Successive approximation register (SAR) ADCs are favored due to their simple structure and high power efficiency^[2]. However, the conversion speed of SAR ADCs is largely limited by their serial decision processes. Moreover, the area increases with the increase of the resolution, especially more than 10-bit. Conventional structures could not meet the system requirement completely. As a result, the study of the innovative ADC structures becomes meaningful.

Recently, pipelined SAR ADCs have been widely researched, which are composed of pipeline ADC and SAR ADC, having a better compromise among the speed, power and resolution^{[3, 4]}. In a pipeline ADC, a large first stage MDAC resolution improves the overall ADC linearity and relaxes noise and matching requirements, because the errors from the later stages are divided by the large inter-stage gain. However, the area and power of the first stage MDAC increase with the augment of the resolution exponentially because of the flash sub-ADC. The architecture proposed here uses SAR for the sub-ADCs, instead of the conventional flash architecture, which makes the high-resolution MDAC possible. In addition, the SAR sub-ADC, which halves in resolution, also has a better performance in speed and area compared with an SAR ADC. Reference ^[3] proposed a 12-bit 50 MS/s ADC using a typical two-stage pipelined SAR structure. However, the switching scheme of the SAR ADC is conventional which needs a lot of improvement to achieve better performance. The reported pipelined SAR ADC in Reference ^[4] introduces a 1.5-bit/cycle algorithm into the sub-SAR ADC to release the comparator offset constraint. However, the architecture occupies a lot more circuit blocks in order to achieve 1.5-bit/cycle algorithm.

This paper proposes a two-stage pipelined SAR ADC architecture which pipelines a 5-bit SAR-based MDAC with a 6b SAR ADC. Several key techniques are presented in this work to further reduce the power consumption. The gain of the first stage MDAC is halved to reduce the op-amp demand and power consumption in the first stage. The 1b redundancy digital error correction method relaxes the requirement for the first stage sub-ADC decision in accuracy. As a result, the two-stage fully dynamic comparator is used to improve the comparator speed without static power consumption. SAR dynamic control logic circuits offer a better performance in speed, area and power consumption by using a dynamic logic unit instead of a shifting register and flip-flop.

2. ADC architecture and technique

Figure 1 shows the ADC architecture and timing diagram. It comprises a 5-bit SAR ADC, a residue amplifier and a 6-bit SAR ADC without a dedicated front-end S/H. The first 5-bit capacitive-DAC (CDAC) in the sub-ADC also functions as the input sampling capacitance to reduce the area and eliminate mismatch compared with the conventional pipeline ADC, which has an additional front-end S/H. The first stage SAR logic converts the coarse 5-bit code and generates the residue on the top plate of the first stage CDAC, which is amplified by 8 to the second stage CDAC. Then, the second stage SAR ADC generates the 6-bit fine code, while the first stage generates the next 5-bit coarse code. Finally, the digital error correction logic codes the 5-bit coarse and 6-bit fine codes to output the 10-bit code.

In a conventional pipeline ADC, 0.5-bit redundancy is needed to correct the decision error generally, which can eliminate the data overflow and reduce power and area by removing the top comparator in the flash sub-ADC. However, in a pipelined SAR ADC it should take extra time and circuit overhead to level shift the signals to achieve 0.5-bit redundancy instead of simply removing the top comparator^[4]. Figure 2 shows the principle of the 1-bit redundancy digital error correction method used in this paper. The 1-bit redundancy addition will induce an offset voltage of $\frac{1}{16}V_{\rm ref}$, resulting in the output digital range from “js-37-06-13710000” to “1js-37-06-13701111”. This offset can be eliminated by the digital correction easily, not increasing the complexity of the circuit.

3. Circuit implementation

3.1 First-stage 5 b half-gain MDAC

Figure 3 shows the block diagram of the first stage MDAC. The architecture is fully differential to achieve high accuracy. To reduce the switching energy, the $V_{\rm cm}$-based switching procedure is employed^[5] The input common-mode voltage remains $V_{\rm cm}$ in all phases, which ensures the ADC linearity. The differential input signal is sampled on the top plate of the CDAC, which halves the capacitor array compared with the conventional bottom sampling, when $\phi _1$ is high. At the same time, the feedback capacitor $C_{\rm F}$ is reset. As $\phi_2$ is high, the residue on the top plate of the CDAC is amplified by the amplifier. The value of the unit capacitor is 24.3 fF $(5 \times 5$ μm²) resulting in the total sampling capacitance of 777.6 fF, to meet the demand for the KT/C noise and capacitor matching.

For the first stage 5 b MDAC, the stage gain is 16 in the conventional pipeline stage, leading to a large open-loop gain demand for the op-amp. This paper utilizes the “half-gain” technology to halve the gain of the 5 b MDAC from 16 to 8. As a result, the feedback factor has an approximately two-fold increase so that the op-amp bandwidth can be decreased two-fold for the same settling error. In addition, the output swing is also halved by the “half-gain” technology, which relaxes the op-amp design for the output swing, from which more cascode transistors can be cascaded in the op-amp to enhance the op-amp gain. For a 10 b two-stage pipelined SAR ADC, a low gain of 66 dB is required for the op-amp. As its low requirement, a simple folded cascode op-amp structure is used here adequately, shown in Figure 4.

3.2 Second-stage 6 b SAR ADC

Figure 5 shows the block diagram and timing diagram of the second stage 6-bit SAR ADC. When φ_SAR2 is high, switches Sp1 and Sp2 turn on to sample the amplified residue on the top plate of the CDAC, then the sampled voltages are quantized by the SAR logic when φ _SAR2 is low. The clock φ _SAR2 is ahead of the first stage MDAC clock φ₂ to ensure an accurate sampling. Due to the “half-gain” technology, the SAR ADC requires half-reference voltage ($V_{\rm ref}$/2). An additional capacitor is introduced to get $V_{\rm ref}$/2 without an appropriative voltage in Reference ^[3]. However, it would double the whole capacitance as the load of the first stage MDAC, and aggrandizes the area of the second stage. This work has a specialized half-reference voltage in the first stage, which is reused in the second stage. The second stage SAR ADC only needs 6-bit accuracy with 1 b redundancy for digital error correction, and the noise contribution of the second stage is almost eliminated by the large first stage MDAC gain of\, 8. As a result, the nonlinearity caused by the dynamic offset and the parasitic capacitance variation of the comparator is also of little concern for this reason. Thus, the set and down switching technique is induced to simplify the second stage^[6]. The unit capacitor can also scale down, and its value is 15.5 fF (4 × 4 μm²) leading to the total sampling capacitance of 496 fF.

3.3 Fully dynamic comparator

Figure 6 shows the schematic of the two-stage fully dynamic comparator, which is both used in the first and second stages to simplify design, but with respective sizes of transistors optimized for a different accuracy and speed. A pre-amplifier is mandatory to insure proper switching of the latch since the comparator input voltage difference is small. During the reset phase when Clkc is high and Clkcb is low, the tail M₀ is turned off, M₃/M₄ pulls AN/AP to ground respectively. Simultaneously, the comparator outputs OUTN and OUTP are reset to VDD. When Clkc turns to low in the regeneration phase, M₀ is turned on, the input differential pair M₁ and M₂ charge the nodes AN and AP at a rate depending on the input signal difference $(V_{\rm inp}-V_{\rm inn})$. Once either of the nodes approximates the threshold voltage of the input transistors of the latch stage, the latch regeneration forces one output to high and the other to low. As the output voltage increases, the positive feedback system is activated and finally provides the rail-to-rail output. The circuit only consumes power in the regeneration phase, so that the average power consumption of the comparator is very low.

3.4 SAR control logic

The proposed ADC utilizes a dynamic SAR logic, as shown in Figure 7. Compared to the conventional approach using flip-flop, dynamic logic is utilized to reduce the number of transistors and nodes, thus offering a better performance in speed and in power consumption^{[7, 8]}. In this work, the outputs P and N are kept by a simple regenerative feedback, ensuring the reliability of the output.

At the sampling phase, all the outputs (Pi and Ni) are reset to low by M₈ and M₁₂. After that, signal D is turned to high and Clk is pulled down to ground. Meanwhile, signals P and N store the comparator outputs CMPN and CMPP by the regenerative feedback of M₉ and M₁₁. Signal Q is charged to $V_{\rm DD}$ as soon as it comes to the falling edge of Valid, indicating that this operation is completed, which turns into the signal D of the next dynamic logic. M₁₃ and M₁₄ are used to latch the signals CMPN and CMPP even if the comparator outputs change afterward.

4. Experiment results

The proposed ADC was fabricated using SMIC 180 nm CMOS technology, and the active area of the ADC core is about 0.16 mm², as shown in Figure 8. Figure 9 shows the measured 8192-point FFT spectrum of the proposed pipelined SAR ADC with an input frequency of 15 MHz at 50 MHz sampling rate under a supply voltage of 1.8 V. The proposed ADC draws 5 mW and the measured SNDR is 56.04 dB, corresponding to an ENOB of 9.02-bit. Figure 10 plots the dynamic ranges SNDR and SFDR at different sampling frequencies. SNDR and SFDR remain virtually unchanged when the input frequency varies within the range of Nyquist rate. Therefore, the effective resolution bandwidth can reach the Nyquist frequency. Figure 11 shows the measured DNL and INL of the proposed ADC. The peak DNL and INL are 0.9/-0.8 LSB and 1.32/-1.43 LSB, respectively.

Table 1 summarizes the performance of the proposed ADC, and shows the performance comparison between our work and previous reported ADCs^{[4, 9, 10]} As can be seen in Table 1, the performance of the pipelined SAR ADC is between pipeline ADC and SAR ADC, and its area may have advantages. The power efficiency of the proposed ADC is still competitive when it is implemented in 0.18 μm standard process.

5. Conclusion

In this work, a 10 bit two-stage pipelined SAR ADC in 180 nm CMOS process is presented. The ADC achieves 9.02 ENOB with a power consumption of 5 mW at a sampling rate of 50 MS/s and a supply voltage of 1.8 V. The high performance is achieved by utilizing SAR ADC instead of the flash ADC. The measurement results have demonstrated that the proposed ADC circuit has a considerable performance and can replace the conventional constructions.