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J. Semicond. > 2017, Volume 38 > Issue 2 > 024004

SEMICONDUCTOR DEVICES

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

Huifang Xu1, and Yuehua Dai2

+ Author Affiliations

 Corresponding author: Huifang Xu, Email:xu0342@163.com

DOI: 10.1088/1674-4926/38/2/024004

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Abstract: A two-dimensional analytical model of double-gate (DG) tunneling field-effect transistors (TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.

Key words: double-gate tunnel field effect transistor (TFET)interface trapped chargesanalytical model

The tunnel field effect transistors (TFETs) are one of the promising devices to replace metal-oxide semiconductor field effect transistors (MOSFETs) for ultralow-power applications, which is because they can allow a lower off-state leakage current due to the reduced electric field at the tunnel junction in the off-state, lower subthreshold swing (SS), and better immunity towards short channel effects (SCEs)[1-4]. However, the on-state current ( Ion) is lower than that of the MOSFET, and ambipolar behavior will degrade the performance of the TFET, which are the two major problems of this device[5]. Therefore, TFETs since their introduction have been extensively studied focusing on boosting Ion [6-8] and suppressing ambipolar current[9]. On the other hand, as far as the reliability of the TFET is concerned, the interface trapped charges is one of the critical issues due to the change in tunneling field, which can bring an overall increase or decrease in the drain current of the TFET, leading to a change in the threshold voltage of the TFET. So many works on interface trapped charges in TFET have been reported in the recent literature[10-12].

However, an accurate model is helpful to better study the device physics for further improvement and scaling. The reported potential model is based on the analytical solution of the Poisson equation[13, 14]. On the one hand, the whole channel is assumed to be fully depleted and it ignores the effect of channel mobile carrier density in the solution of Poisson's equation[15], but it is incorrect when the device is operated in the linear state. This is because of the debiasing effect of channel mobile charges. However, many mobile charges exist in the channel in this state[16]. Therefore, it is necessary to consider the channel mobile charge term in the Poisson equation. Furthermore, the polynomial approximation in the above mentioned model is generally used for the solution of the Poisson equation, which will lead to a large error when the thickness of the silicon film is much larger than the gate-oxide thickness, or the gate-oxide thickness is much larger than the thickness of the silicon film. On the other hand, the model presents the solution of the Poisson equation with consideration of the mobile charge term[17], but the lateral electric field does not agree with the simulation result due to considering only the first-order eigenfunction. Moreover, as far as we know, the impacts of both the interface trapped charges and the channel mobile charges on TFET have never been reported up to now.

Based on the above analysis, we present a more accurate and physical-based analytical model of DG TFET in order to overcome the above mentioned shortcomings of the reported models, which consider the effects of both the interface trapped charges and the channel mobile charges, simultaneously. The superposition principle is used to solve the non-linear Poisson equation. From the surface potential profile, the electric field can be obtained. Using Kane's model, the drain current can also be obtained.

Fig. 1 shows the cross-sectional schematics of the proposed DG TFET with interface trapped charges. C1 and C2 are damaged and undamaged channel regions, L1 and L2 are the lengths of the two regions, respectively. L is the length of the channel, ts is the silicon film thickness, tox is the gate-oxide thickness. Unless otherwise indicated, the channel is nearly intrinsic (doping concentration =1016 cm 3) , while p + source region and n + drain region are heavily doped as 10 20 and 5 × 10 18 cm 3 , respectively.

Figure  1.  (Color online) Cross-sectional schematics of DG TFET including localized interface charges.

The channel electrostatic potential, ϕi(x,y) , is governed by the two-dimensional (2D) Poisson equation including channel mobile charge density, where i=1,2 represents the regions C1 and C2 , respectively, V is the electron quasi-Fermi potential, ni is the intrinsic carrier density, εSi is the permittivity of the silicon, Vt=kT/q is the thermal voltage, q is the electronic charge.

2ϕi(x,y)x2+2ϕi(x,y)y2=qεSiniexp[ϕi(x,y)VVt],i=1,2.

(1)

Using the superposition principle, the potential ϕi(x,y) can be written as

ϕi(x,y)=ϕ0i(y)+ϕ1i(x,y),

(2)

where ϕ0i(y) is the solution of one-dimensional (1D) Poisson equation in the channel depth direction (y) . The 1D Poisson equation is expressed as

2ϕ0i(y)y2=qεsiniexpϕ0i(y)VVt.

(3)

The corresponding boundary conditions of ϕ0i(y) are

ϕ0i(y)y|y=0=0,

(4)

Cox(VgsVFBiϕ0i(t0))=εSiϕ0i(y)y|y=t0,

(5)

where t0=tSi/2 , so ϕ0i(y) is obtained as

ϕ0i(y)=V+Vtln[B2i2δsec2(Biy/t0)],

(6)

where δ=qnit20/(4εsiVt) , V in the channel length direction (x) stays constant (the value is equal to VDS ) except near the source junction[17].

Combining Eq. (6) with the boundary condition Eq. (5), the new equation about Bi can be established as

2εsiVtt0Bitan(Bi)+CoxVtln[B2i2δsec2(Bi)]=Cox(VgsVFBiV),

(7)

where VFBi is the flat-band voltage, VFB1=ϕmsqNf/Cox , VFB2=ϕms. Cox is the gate oxide capacitance, Nf is the interface trapped charge sheet density.

The 2D Laplace equation about ϕ1i(x,y) is written as

2ϕ1i(x,y)x2+2ϕ1i(x,y)y2=0,i=1,2.

(8)

Using the separation of variables method, the potential ϕ1i(x,y) can be expressed as

ϕ1i(x,y)=[aiexp(λx/t0)+biexp(λx/t0)]cos(λy/t0),

(9)

where ai , bi are the unknown coefficients and λ is the eigen value.

The corresponding boundary conditions of ϕ1i(x,y) in Eq. (9) are

ϕ11(x,y)|x=0=VSϕ01(y),

(10)

ϕ11(x,y)|x=L1=VPϕ01(y),

(11)

ϕ12(x,y)|x=L=VDϕ02(y),

(12)

Coxϕ1i(x,t0)=εSiϕ1i(x,y)y|y=t0,

(13)

where VS=kTqlnNSni and VD=Vds+kTqlnNDni are the source potential and the drain potential, respectively, VP is the surface potential at the border of the C 1 and C 2 regions.

The value of λ is obtained by combining Eq. (9) with the boundary condition Eq. (13)

λtan(λ)=Coxt0εsi.

(14)

Combining Eq. (9) with the boundary conditions Eqs. (10) and (11), two new equations can be established as

m=1(a1+b1)cos(λmy/t0)=VSϕ01(y).

(15)

m=1[a1exp(λmL1/t0)+b1exp(λmL1/t0)]cos(λmy/t0)=VPϕ01(y).

(16)

Eqs. (15) and (16) are solved using Fourier series solution, two new equations about the coefficients a1 and b1 are expressed as

a1+b1=VSsin(λ)V10.5λ+0.25sin(2λ),

(17)

a1exp(λL1/t0)+b1exp(λL1/t0)=VPsin(λ)V10.5λ+0.25sin(2λ),

(18)

where the value of V1 is V1=λcos(λ/)ϕ01(y)|y=0.5t0 .Combining Eq. (17) with Eq. (18), the value of coefficients a1 and b1 can be calculated as

a1=(VPVSexp(λL1/t0))sin(λ)V1(1exp(λL1/t0))(λ+0.5sin(2λ))sinh(λL1/t0),

(19)

b1=(VPVSexp(λL1/t0))sin(λ)+V1(1exp(λL1/t0))(λ+0.5sin(2λ))sinh(λL1/t0).

(20)

Combining Eq. (9) with the boundary conditions Eqs. (11) and (12), the above approach can be used to solve the parameters a2 and b2 ,

a2=({VDexp(λL1/t0)VPexp[λ(L1+L2)/t0]}sinλ+V2{exp[λ(L1+L2)/t0]exp(λL1/t0)})×[(λ+0.5sin2λ)sinh(λL2/t0)]1,

(21)

b2=({VDexp(λL1/t0)+VPexp[λ(L1+L2)/t0]}sinλV2{exp[λ(L1+L2)/t0]exp(λL1/t0)})×[(λ+0.5sin2λ)sinh(λL2/t0)]1,

(22)

where the value of V2 is λcos(λ/2)ϕ02(y)|y=0.5t0 . Moreover, electric flux at the interface of the C 1 and C 2 regions is continuous,

ϕ1x|x=L1=ϕ2x|x=L1,

(23)

so the value of VP is obtained from Eqs. (9), (14) and (20)-(23) as

VP={sin(λ)[VDsinh(λL1/t0)+VSsinh(λL2/t0)]+V1[sinh(λL2/t0)cosh(λL1/t0)sinh(λL2/t0)]+V2[sinh(λL1/t0)cosh(λL2/t0)sinh(λL1/t0)]}×{sinλ[sinh(λL2/t0)cosh(λL1/t0)+sinh(λL1/t0)cosh(λL2/t0)]}1.

(24)

To calculate the drain current of TFET, the most widely used model is the Kane model using the average electric field ( ˉE ) along the shortest tunneling length ( LT) . The potential so obtained [Eqs. (6) and (9)] is then used to derive the electric field of TFET,

Exi=ϕ1i(x,y)/x=(aiλ/t0exp(λx/t0)biλ/t0exp(λx/t0))cos(λy/t0),

(25)

Eyi=mdϕ0i(y)/dyϕ1i(x,y)/y=2VtBi/t0tan(Biy/t0)+λ/t0(aiexp(λx/t0)+biexp(λx/t0))sin(λy/t0).

(26)

Since the lateral electric field along the channel is assumed to be constant in the channel depth, thus, ˉE can be evaluated using the follow expression[18],

ˉE=EdxLT=|Exi|2+|Eyi|2dxLT,

(27)

LT lies between the source and the point in the channel where the surface potential increases by EG/q , so it can be evaluated as LT=x(EG/q+ϕ1(0,t0))x(ϕ1(0,t0)) , thus the expression of LT is

LT=t0λln({[Vs+EG/qϕ01(t0)]/cosλ+{[Vs+EG/qϕ01(t0)]/cosλ}24a1b1}×(2a1)1).

(28)

The channel width is Wch in the model and simulation in this paper, so the drain current is expressed as [17]

IDS=qtsLTWchAˉE2.5exp(BˉE),

(29)

where A and B are the tunneling process-dependent parameters, the parameters provided in the simulation tool, TCAD device simulator Silvaco[19] are A=4×1014cm1/2 V 5/2 s 1 and B=1.9×107 V/cm[20], and the parameters of silicon are extracted from experimental data of a p-n tunneling diode[21].

Threshold voltage is an important parameter for TFET. The threshold voltage is known as the critical value of the gate voltage, in which the conduction band of the source and the valence band of the channel are in line with each other[22]. It can be extracted using several approaches such as constant current (CC) method and peak transconductance change (TC) method[23]. But CC method uses an optimized value of drain current which may not provide an accurate threshold voltage for TFET and carry less practical meaning. The threshold of TFET in TC method is defined as the value of the gate voltage which corresponds to the maximum of the 1st order differentiation of transconductance dgm/dVgs . The advantage of this method is that it detects the gate voltage where the shortest tunneling length gets saturated, and it exhibits the transition between strong and weak controls of the tunneling barrier width. On the basis of Eq. (29), the transconductance of TFET can be obtained by the 1st order differentiation of drain current w.r.t. gate-source voltage for a constant drain-source voltage and it is expressed as

gm=dIDSdVgs=qtsAˉE2exp(BˉE)dLTdVgs+2qtsALTˉEexp(BˉE)dˉEdVgs+qtsALTˉE2dexp(BˉE)dVgs.

(30)

But a lot of parameters in Eq. (30) w.r.t. LT and ˉE are related to Vgs , so it is not easy to write the analytical expression about gm and dgm/dVgs as the function of Vgs . However, the tunneling barrier width at the tunnel junction in this state has a transition between the strong and weak dependence on the gate voltage. Therefore, we can calculate the threshold voltage based on the saturation of shortest tunneling distance.

The cross-sectional schematics of the proposed DG TFET with interface trapped charges, which is shown in Fig. 1, is used in verifying the model against the simulation results. Simulations in this paper are performed using the TCAD device simulator Silvaco, the physical models embodied in our simulations are listed as follows: non-local trap-assisted tunneling model (tat.nonlocal), non-local band-to-band tunneling model (bbt.nonlocal), inclusion of non-local derivatives in the Jacobian matrix (bbt.nlderivs), Shockley-Read-Hall (SRH) recombination model, auger carrier recombination, Wentzel-Kramers-Brillouin (WKB) model with Fermi statistics, and bandgap narrowing model (bgn).

Fig. 2 shows the calculated potential profile of the DG TFET including interface trapped charges, which is distributed at the gate-oxide layer and the silicon film interface, where L1=10 nm, Nf=1012 {cm} 2 , Vgs is swept from 0 to 2.0 V and Vds is fixed at 1 V. When Vgs is increased from 0 to 1 V, the whole channel (regions C 1 and C 2) is assumed to be fully depleted, the surface potential increases with Vgs . However, when Vgs is substantially high, the surface potential in the region C 2 becomes independent of Vgs and it is pinned at drain potential, namely, Ucsat=Vds+(kT/q)ln(Nd/ni) . This is because the mobile charge in the region C 2 screens the surface potential from further bending.

Figure  2.  (Color online) Surface potential of DG TFET for different gate--source biases.

Fig. 3 shows the surface potential of DG TFET with different value of the interface trapped charge sheet density. From Fig. 3, we can find the variation of Nf brings the larger difference in the surface potential in the region C 1 , this is due to the fact that the value of Nf will change the value of VFB1 . When the value of Nf is positive, VFB1 is decreased by a factor of qNf/Cox , thus the effective gate bias increases under the region C 1 . However, when the value of Nf is negative, VFB1 is increased by a factor of qNf/Cox , thus the effective gate bias reduces under the region C 1 . Therefore, Nf will change the values of B1 and ϕ01(y) , as shown in Eq. (6). Meanwhile, it will impact on the values of a1 , b1 , a2 , b2 , and VP , but these values have a minor effect on the surface potential of the region C 2 . This is due to the fact that interface trapped charges located above the region C 1 will induce the change of the transverse electric field, the presence of the positive interface trapped charge sheet density will slightly enhance the field in the region C 1 , whereas, the electric field in the region C 1 is effectively suppressed by the negative interface trapped charge sheet density, and the enhanced and the suppressed field in the region C 1 affected the channel mobile charge carriers, but it has a minor effect on the channel mobile carriers of the region C 2 . A good agreement is found between the model predictions and the simulated results for different polarity interface trapped charge sheet density.

Figure  3.  (Color online) Surface potential of DG TFET for different Nf .

The transverse electric field of DG TFET with interface trapped charge sheet density is shown as Fig. 4, which shows a non-uniform electric field along the channel, the peak value of the transverse electric field lies on the source-channel junction, and then it gradually decreases to its minimum value at the middle of the channel. However, the transverse electric field peak value of the reported models is at the middle of the channel due to considering only the first-order eigenfunction [17], which is not consistent with the electric field characteristic of DG TFET. In order to overcome the precision and simplicity, a fitting parameter is adopted in the reported electric field model. But in our model, it can also be very accurately reflected in the characteristics of the device without fitting parameter and with small calculating amount.

Figure  4.  Transverse electric field of DG TFET with Nf .

Fig. 5 shows surface potential profile of DG TFET with different values of L1 . From Eq. (6), we can find that 1D surface potential, i.e., ϕ0i(t0) , is not affected by L1 . For example, using the parameters of , Fig. 5, the calculated results of ϕ01(t0) and ϕ02(t0) are 1.38 and 1.33 V, respectively. On the other hand, L1 can influence the values of a1 , b1 , a2 , b2 , and VP , as shown in the Eqs. (19) -(24), but the impact on the 2D surface potential, i.e., ϕ1i(x,t0) , can be ignored. Therefore, the major difference lies in the surface potential in the region C 1 .

Figure  5.  (Color online) Surface potential for DG TFET with different L1 .

Fig. 6 shows the shortest tunneling length (LT) for DG TFET with different interface trapped charge sheet density (Nf) according to Eq. (28). As the applied gate-source voltage increases, the major charge carrier tunnel through the source-channel interface and thus LT reduces due to superior gate control gradually and gets saturated eventually. Under the same value of gate-source voltage, LT decreases with increasing Nf . This is due to the large value of Nf that leads to a large surface potential in the region C 1 as depicted in Fig. 3 and small LT .

Figure  6.  (Color online) Shortest tunneling length of DG TFET with different Nf .

The shortest tunneling length (LT) for DG TFET with interface trapped charge as a function of gate-source voltage for different εox , ts , and tox are displayed in Figs. 7(a), 7(b), and 7(c). As the gate-oxide dielectric constant (εox) increased and gate-oxide thickness (tox) downscaled, the capacitive coupling effect between gate and channel is improved and thus reduces LT for a constant drain-source voltage. Similarly, LT reduces with decreasing silicon film thickness (ts) because the impact of gate-source voltage on channel increases at small ts . The reduction in LT at a constant gate-source voltage improves tunneling current due to larger tunneling volume.

Figure  7.  (Color online) Shortest tunneling length of DG TFET with (a) different εox , (b) different ts , (c) different tox .

Fig. 8 shows the transfer characteristics curve in logarithmic scale for DG TFET with different interface trapped charge sheet density (Nf) for a constant drain-source voltage. As discussed earlier, the value of Nf will change the transverse electric field in the region C 1 slightly. A small modification of the transverse electric field has impact on LT , giving rise to the dramatic change of the drain current, due to the exponential 1/E dependence of tunneling rate in Eq. (29). However, when gate-source voltage reaches a certain value, gate-source voltage has a minor effect on LT as depicted in Fig. 6, so the change of the drain current becomes small. Moreover, the positive polarity of Nf shifts the transfer characteristics curve to the left, which suggests that it requires less LT for the same drain current, confirming increased electric field at the tunneling junction. Moreover, the proposed model used the corresponding device parameters in Ref. [24] that have been calibrated with the experimental data [Fig. 7] available for a vertical DG PIN TFET, and we find that the proposed model of the drain current resembles the experimental result.

Figure  8.  (Color online) Drain current as a function of gate-source voltage for DG TFET with different Nf .

In this paper, the simulation result of the threshold voltage is extracted using the peak value of change in transconductance curve as shown in Fig. 9(a). The model result of the threshold voltage is defined as the gate voltage for which the shortest tunneling distance gradually starts to saturate with the applied gate bias. The threshold voltage for DG TFET with different polarity interface trapped charge density (Nf) is shown as Fig. 9(b), we can find that the presence of Nf can increase or decrease the threshold voltage. This is due to the fact that the presence of Nf can change the value of LT as depicted in Fig. 6.

Figure  9.  (a) Extraction of threshold voltage of DG TFET by peak transconductance change method, (b) threshold voltage of DG TFET with different Nf .

Fig. 10 illustrates the threshold voltage variation of DG TFET with interface trapped charge as a function of gate-oxide dielectric constant, silicon film thickness, and gate-oxide thickness at Vgs= 2.0 V and Vds= 1.0 V. The threshold voltage variation in DG TFET is sensitive to the gate-oxide dielectric constant, and gate-oxide thickness, low threshold voltage is obtained for large gate-oxide dielectric constant or small gate-oxide thickness, because of the better capacitive control of the tunneling barrier width at the source-channel interface. Similarly, when the silicon film thickness is scaled down from 15 to 5 nm with other parameters fixed, the threshold voltage will reduce as the narrowing of the shortest tunneling length saturates, as shown in Fig. 7(b). The proposed method of extraction of the threshold voltage resembles the simulated result.

Figure  10.  Threshold voltage of DG TFET with (a) different εox , (b) different ts , (c) different tox .

In this paper, an accurate analytical modeling approach including the effect of the channel mobile charge carriers to analyze the impact of the interface trapped charges on the device performance of DG TFET is proposed. The model analyzes the effects of the interface trapped charges density, and the length of damaged region on the surface potential, and drain current. The gate threshold voltage is further extracted using proposed transconductance change method based on the saturation of shortest tunneling distance. The proposed model is a generic model, which can not only be extended to other structures, such as silicon-on-insulator (SOI) TFET, DMG TFET, TMG TFET and NW TFET, the dependence of the surface potential, the shortest tunneling length, drain current, and threshold voltage on the parameters of these different structure devices by varying gate-oxide thickness, silicon film thickness and gate-oxide dielectric constant can also be analyzed, but also can be used to analyze and design the charge-trapped memory based on TFET.



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Fig. 1.  (Color online) Cross-sectional schematics of DG TFET including localized interface charges.

Fig. 2.  (Color online) Surface potential of DG TFET for different gate--source biases.

Fig. 3.  (Color online) Surface potential of DG TFET for different Nf .

Fig. 4.  Transverse electric field of DG TFET with Nf .

Fig. 5.  (Color online) Surface potential for DG TFET with different L1 .

Fig. 6.  (Color online) Shortest tunneling length of DG TFET with different Nf .

Fig. 7.  (Color online) Shortest tunneling length of DG TFET with (a) different εox , (b) different ts , (c) different tox .

Fig. 8.  (Color online) Drain current as a function of gate-source voltage for DG TFET with different Nf .

Fig. 9.  (a) Extraction of threshold voltage of DG TFET by peak transconductance change method, (b) threshold voltage of DG TFET with different Nf .

Fig. 10.  Threshold voltage of DG TFET with (a) different εox , (b) different ts , (c) different tox .

[1]
Bardon M G, Neves H P, Puers R, et al. Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans Electron Devices, 2010, 57(4):827 doi: 10.1109/TED.2010.2040661
[2]
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    Huifang Xu, Yuehua Dai. Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers[J]. Journal of Semiconductors, 2017, 38(2): 024004. doi: 10.1088/1674-4926/38/2/024004
    H F Xu, Y H Dai. Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers[J]. J. Semicond., 2017, 38(2): 024004. doi: 10.1088/1674-4926/38/2/024004.
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    Received: 23 May 2016 Revised: 06 July 2016 Online: Published: 01 February 2017

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      Huifang Xu, Yuehua Dai. Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers[J]. Journal of Semiconductors, 2017, 38(2): 024004. doi: 10.1088/1674-4926/38/2/024004 ****H F Xu, Y H Dai. Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers[J]. J. Semicond., 2017, 38(2): 024004. doi: 10.1088/1674-4926/38/2/024004.
      Citation:
      Huifang Xu, Yuehua Dai. Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers[J]. Journal of Semiconductors, 2017, 38(2): 024004. doi: 10.1088/1674-4926/38/2/024004 ****
      H F Xu, Y H Dai. Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers[J]. J. Semicond., 2017, 38(2): 024004. doi: 10.1088/1674-4926/38/2/024004.

      Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

      DOI: 10.1088/1674-4926/38/2/024004
      Funds:

      the University Natural Science Research Key Project of Anhui Province KJ2016A169

      the National Natural Science Foundation of China 61376106

      the Introduced Talents Project of Anhui Science and Technology University 

      Project supported by the National Natural Science Foundation of China (No. 61376106), the University Natural Science Research Key Project of Anhui Province (No. KJ2016A169), and the Introduced Talents Project of Anhui Science and Technology University

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      • Corresponding author: Huifang Xu, Email:xu0342@163.com
      • Received Date: 2016-05-23
      • Revised Date: 2016-07-06
      • Published Date: 2017-02-01

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