1. Introduction
The tunnel field effect transistors (TFETs) are one of the promising devices to replace metal-oxide semiconductor field effect transistors (MOSFETs) for ultralow-power applications, which is because they can allow a lower off-state leakage current due to the reduced electric field at the tunnel junction in the off-state, lower subthreshold swing (SS), and better immunity towards short channel effects (SCEs)[1-4]. However, the on-state current (
However, an accurate model is helpful to better study the device physics for further improvement and scaling. The reported potential model is based on the analytical solution of the Poisson equation[13, 14]. On the one hand, the whole channel is assumed to be fully depleted and it ignores the effect of channel mobile carrier density in the solution of Poisson's equation[15], but it is incorrect when the device is operated in the linear state. This is because of the debiasing effect of channel mobile charges. However, many mobile charges exist in the channel in this state[16]. Therefore, it is necessary to consider the channel mobile charge term in the Poisson equation. Furthermore, the polynomial approximation in the above mentioned model is generally used for the solution of the Poisson equation, which will lead to a large error when the thickness of the silicon film is much larger than the gate-oxide thickness, or the gate-oxide thickness is much larger than the thickness of the silicon film. On the other hand, the model presents the solution of the Poisson equation with consideration of the mobile charge term[17], but the lateral electric field does not agree with the simulation result due to considering only the first-order eigenfunction. Moreover, as far as we know, the impacts of both the interface trapped charges and the channel mobile charges on TFET have never been reported up to now.
Based on the above analysis, we present a more accurate and physical-based analytical model of DG TFET in order to overcome the above mentioned shortcomings of the reported models, which consider the effects of both the interface trapped charges and the channel mobile charges, simultaneously. The superposition principle is used to solve the non-linear Poisson equation. From the surface potential profile, the electric field can be obtained. Using Kane's model, the drain current can also be obtained.
2. Device structure and model
Fig. 1 shows the cross-sectional schematics of the proposed DG TFET with interface trapped charges.
2.1 Calculation of potential distribution
The channel electrostatic potential,
∂2ϕi(x,y)∂x2+∂2ϕi(x,y)∂y2=qεSiniexp[ϕi(x,y)−VVt],i=1,2. |
(1) |
Using the superposition principle, the potential
ϕi(x,y)=ϕ0i(y)+ϕ1i(x,y), |
(2) |
where
∂2ϕ0i(y)∂y2=qεsiniexpϕ0i(y)−VVt. |
(3) |
The corresponding boundary conditions of
∂ϕ0i(y)∂y|y=0=0, |
(4) |
Cox(Vgs−VFBi−ϕ0i(t0))=εSi∂ϕ0i(y)∂y|y=t0, |
(5) |
where
ϕ0i(y)=V+Vtln[B2i2δsec2(Biy/t0)], |
(6) |
where
Combining Eq. (6) with the boundary condition Eq. (5), the new equation about
2εsiVtt0Bitan(Bi)+CoxVtln[B2i2δsec2(Bi)]=Cox(Vgs−VFBi−V), |
(7) |
where
The 2D Laplace equation about
∂2ϕ1i(x,y)∂x2+∂2ϕ1i(x,y)∂y2=0,i=1,2. |
(8) |
Using the separation of variables method, the potential
ϕ1i(x,y)=[aiexp(λx/t0)+biexp(−λx/t0)]cos(λy/t0), |
(9) |
where
The corresponding boundary conditions of
ϕ11(x,y)|x=0=VS−ϕ01(y), |
(10) |
ϕ11(x,y)|x=L1=VP−ϕ01(y), |
(11) |
ϕ12(x,y)|x=L=VD−ϕ02(y), |
(12) |
−Coxϕ1i(x,t0)=εSi∂ϕ1i(x,y)∂y|y=t0, |
(13) |
where
The value of
λtan(λ)=Coxt0εsi. |
(14) |
Combining Eq. (9) with the boundary conditions Eqs. (10) and (11), two new equations can be established as
∑∞m=1(a1+b1)cos(λmy/t0)=VS−ϕ01(y). |
(15) |
∞∑m=1[a1exp(λmL1/t0)+b1exp(−λmL1/t0)]cos(λmy/t0)=VP−ϕ01(y). |
(16) |
Eqs. (15) and (16) are solved using Fourier series solution, two new equations about the coefficients
a1+b1=VSsin(λ)−V10.5λ+0.25sin(2λ), |
(17) |
a1exp(λL1/t0)+b1exp(−λL1/t0)=VPsin(λ)−V10.5λ+0.25sin(2λ), |
(18) |
where the value of
a1=(VP−VSexp(−λL1/t0))sin(λ)−V1(1−exp(−λL1/t0))(λ+0.5sin(2λ))sinh(λL1/t0), |
(19) |
b1=−(VP−VSexp(λL1/t0))sin(λ)+V1(1−exp(λL1/t0))(λ+0.5sin(2λ))sinh(λL1/t0). |
(20) |
Combining Eq. (9) with the boundary conditions Eqs. (11) and (12), the above approach can be used to solve the parameters
a2=({VDexp(−λL1/t0)−VPexp[−λ(L1+L2)/t0]}sinλ+V2{exp[−λ(L1+L2)/t0]−exp(−λL1/t0)})×[(λ+0.5sin2λ)sinh(λL2/t0)]−1, |
(21) |
b2=({VDexp(λL1/t0)+VPexp[λ(L1+L2)/t0]}sinλ−V2{exp[λ(L1+L2)/t0]−exp(λL1/t0)})×[(λ+0.5sin2λ)sinh(λL2/t0)]−1, |
(22) |
where the value of
∂ϕ1∂x|x=L1=∂ϕ2∂x|x=L1, |
(23) |
so the value of
VP={sin(λ)[VDsinh(λL1/t0)+VSsinh(λL2/t0)]+V1[sinh(λL2/t0)cosh(λL1/t0)−sinh(λL2/t0)]+V2[sinh(λL1/t0)cosh(λL2/t0)−sinh(λL1/t0)]}×{sinλ[sinh(λL2/t0)cosh(λL1/t0)+sinh(λL1/t0)cosh(λL2/t0)]}−1. |
(24) |
2.2 Calculation of drain current and threshold voltage
To calculate the drain current of TFET, the most widely used model is the Kane model using the average electric field (
Exi=∂ϕ1i(x,y)/∂x=−(aiλ/t0exp(λx/t0)−biλ/t0exp(−λx/t0))cos(λy/t0), |
(25) |
Eyi=−mdϕ0i(y)/dy−∂ϕ1i(x,y)/∂y=−2VtBi/t0tan(Biy/t0)+λ/t0(aiexp(λx/t0)+biexp(−λx/t0))sin(λy/t0). |
(26) |
Since the lateral electric field along the channel is assumed to be constant in the channel depth, thus,
ˉE=∫EdxLT=∫√|Exi|2+|Eyi|2dxLT, |
(27) |
LT=t0λln({[Vs+EG/q−ϕ01(t0)]/cosλ+√{[Vs+EG/q−ϕ01(t0)]/cosλ}2−4a1b1}×(2a1)−1). |
(28) |
The channel width is
IDS=qtsLTWchAˉE2.5exp(−BˉE), |
(29) |
where
Threshold voltage is an important parameter for TFET. The threshold voltage is known as the critical value of the gate voltage, in which the conduction band of the source and the valence band of the channel are in line with each other[22]. It can be extracted using several approaches such as constant current (CC) method and peak transconductance change (TC) method[23]. But CC method uses an optimized value of drain current which may not provide an accurate threshold voltage for TFET and carry less practical meaning. The threshold of TFET in TC method is defined as the value of the gate voltage which corresponds to the maximum of the 1st order differentiation of transconductance
gm=dIDSdVgs=qtsAˉE2exp(−BˉE)dLTdVgs+2qtsALTˉEexp(−BˉE)dˉEdVgs+qtsALTˉE2dexp(−BˉE)dVgs. |
(30) |
But a lot of parameters in Eq. (30) w.r.t.
3. Results and discussion
3.1 Potential model validation
The cross-sectional schematics of the proposed DG TFET with interface trapped charges, which is shown in Fig. 1, is used in verifying the model against the simulation results. Simulations in this paper are performed using the TCAD device simulator Silvaco, the physical models embodied in our simulations are listed as follows: non-local trap-assisted tunneling model (tat.nonlocal), non-local band-to-band tunneling model (bbt.nonlocal), inclusion of non-local derivatives in the Jacobian matrix (bbt.nlderivs), Shockley-Read-Hall (SRH) recombination model, auger carrier recombination, Wentzel-Kramers-Brillouin (WKB) model with Fermi statistics, and bandgap narrowing model (bgn).
Fig. 2 shows the calculated potential profile of the DG TFET including interface trapped charges, which is distributed at the gate-oxide layer and the silicon film interface, where
Fig. 3 shows the surface potential of DG TFET with different value of the interface trapped charge sheet density. From Fig. 3, we can find the variation of
The transverse electric field of DG TFET with interface trapped charge sheet density is shown as Fig. 4, which shows a non-uniform electric field along the channel, the peak value of the transverse electric field lies on the source-channel junction, and then it gradually decreases to its minimum value at the middle of the channel. However, the transverse electric field peak value of the reported models is at the middle of the channel due to considering only the first-order eigenfunction [17], which is not consistent with the electric field characteristic of DG TFET. In order to overcome the precision and simplicity, a fitting parameter is adopted in the reported electric field model. But in our model, it can also be very accurately reflected in the characteristics of the device without fitting parameter and with small calculating amount.
Fig. 5 shows surface potential profile of DG TFET with different values of
3.2 Drain current and threshold voltage model validation
Fig. 6 shows the shortest tunneling length
The shortest tunneling length
Fig. 8 shows the transfer characteristics curve in logarithmic scale for DG TFET with different interface trapped charge sheet density
In this paper, the simulation result of the threshold voltage is extracted using the peak value of change in transconductance curve as shown in Fig. 9(a). The model result of the threshold voltage is defined as the gate voltage for which the shortest tunneling distance gradually starts to saturate with the applied gate bias. The threshold voltage for DG TFET with different polarity interface trapped charge density
Fig. 10 illustrates the threshold voltage variation of DG TFET with interface trapped charge as a function of gate-oxide dielectric constant, silicon film thickness, and gate-oxide thickness at
4. Conclusion
In this paper, an accurate analytical modeling approach including the effect of the channel mobile charge carriers to analyze the impact of the interface trapped charges on the device performance of DG TFET is proposed. The model analyzes the effects of the interface trapped charges density, and the length of damaged region on the surface potential, and drain current. The gate threshold voltage is further extracted using proposed transconductance change method based on the saturation of shortest tunneling distance. The proposed model is a generic model, which can not only be extended to other structures, such as silicon-on-insulator (SOI) TFET, DMG TFET, TMG TFET and NW TFET, the dependence of the surface potential, the shortest tunneling length, drain current, and threshold voltage on the parameters of these different structure devices by varying gate-oxide thickness, silicon film thickness and gate-oxide dielectric constant can also be analyzed, but also can be used to analyze and design the charge-trapped memory based on TFET.