1. Introduction

Metal-semiconductor (MS) rectifying contacts with interfacial layer and ohmic contacts are of vital importance for device applications such as metal-oxide-semiconductor field effect transistors (MOSFETs) which are the most important devices for high-density integrated circuits such as microprocessors and semiconductor memories^[1-10]. Because of the technological importance of MIS (metal-insulator-semiconductor) structures, investigation of the electrical properties of these devices at room as well as cryogenic temperatures are very significant. We have selected Al₂O₃ as an insulator layer, because atomic-layer-deposited (ALD) Al₂O₃ has been explored as a gate insulator for GaAs MOSFETs^[10-16]. Our purpose is to investigate the influence of the Al₂O₃ interfacial layer on the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the Au/Ti/n-GaAs structure. Therefore, the I-V and C-V characteristics for the Au/Ti/n-GaAs structures with and without Al₂O₃ interfacial layer were measured, in the measurement temperature range of 60-300 K. For the Schottky contacts, the n-GaAs wafer was placed on a rotating table. Ti (10 nm) Schottky contacts were made using magnetron DC sputter technique, and Au (50 nm) to protect the Ti metallic layer was evaporated as a top layer on the Ti/n-GaAs structure in high vacuum system of 10^-6 Torr. Indium for ohmic contact was realized backside of the GaAs substrate by means of the thermal evaporation at a base pressure of about 10^-6 Torr.

Atomic-layer-deposited ultrathin layers have found applications in the formation of high-quality thin films and insulators for thin-film transistors, interfacial layers for MOSFETs and high-electron mobility transistors, surface passivation layers for channel field effect transistors^[5-16]. The formation of native oxide layer on the semiconductor traditionally cannot completely passivate the active dangling bonds on the surface of the semiconductor substrate. Therefore, the fabrication of high dielectric materials as an interfacial layer at MS interface plays an important role on the performance and quality of the devices. Such an interfacial layer not only prevents the semiconductor substrate from the destruction of the contact metal, but also relieves the electric field reduction in the devices^[10-20]. The comprehensive simulations of Al₂O₃/InGaAs stack performed by Chagarov and Kummel^[21] have demonstrated that the main role of the oxide in forming a passive interface is to saturate the dangling bonds on the semiconductor atoms. Chang et al.^[22] and Hinkle et al.^[23] have reported that the XPS (X-ray photoemission spectroscopy) spectrum only showed a small amount Ga⁺¹, but neither showed Ga⁺³ nor arsenic oxides for ALD Al₂O₃ on in situ grown GaAs (100). However, they observed for the best-cleaned surfaces that the electrically optimized oxide/GaAs interfaces always only have Ga⁺¹ and no Ga⁺³, no As₂, and no arsenic oxides. Furthermore, Chagarov and Kummel^[21] have mentioned that their own results are consistent with the results of Chang et al.^[22]. Hinkle et al.^[23] have showed that the Ga in the interface is bonded to only one oxygen to produce a minimal charge change, that is, they have Ga⁺³ from Ga₂O₃ as well as Ga⁺¹ from Ga₂O^[21-23].

The ALD is a vapor-phase thin film deposition method characterized by alternating exposure cycles of chemical species with self-limiting surface reactions to produce films with accurate and excellent thickness control and uniformity over large substrate areas. Therefore, ALD can produce high-quality films for active channel layer deposition of thin film transistor at low temperatures. When compared to other low-temperature methods, the ALD stands out with its self-limiting growth mechanism which enables the deposition of highly conformal thin films with sub-nanometer thickness control^[10-21]. Again, it has been mentioned by Wu et al.^[24] and Kukli et al.^[25] that the ALD is a surface-controlled, layer-by-layer process for the deposition of thin films with atomic layer accuracy. Each atomic layer formed in the sequential process is a result of saturated surface-controlled chemical reactions. The film thickness control and the quality of the oxide layer by the ALD are also much higher than those deposited by other methods such as sputtering and electron-beam deposition and the plasma-enhanced-chemical-vapor-deposition (PECVD), in terms of uniformity, defect density and stoichiometric ratio of the films. The ALD is a perspective method for depositing gate oxide materials, and it allows the adjustment of film thickness with monolayer precision, in principle, and high conformality and uniformity due to its submonolayer-by-submonolayer deposition mode characteristic^[24-37].

Moreover, Nguyen et al.^[38] and Xuan et al.^[39] have reported that the physical and chemical interfacial properties that have a strong correlation with the GaAs surface conditions are equally important, and the Al₂O₃/GaAs structure shows that the barrier height is strongly affected by the initial conditions of GaAs, and that the density of interfacial defect states can be reduced with a particular surface treatment of GaAs. Furthermore, they^{[38, 39]} have pointed out that As₂O₃ and Ga₂O₃ are formed when a clean GaAs surface is exposed to air, leaving bare arsenic atoms embedded within the native oxide near the oxide/GaAs interface. It is also known that As₂O₃ is mobile at the grain boundaries and induces a nonuniform As₂O₃-rich layer. Such an interfacial layer causes an increase in the overall oxide thickness and carrier scatterings and reduces the escape probabilities of photoelectrons, therefore, leading to a reduction in oxide photocurrents. It has been reported by Chou et al.^[34] that the cross-sectional transmission electron microscopy (TEM) analysis indicates that the samples obtained by ALD of Al₂O₃ onto native GaAs oxide for faces of GaAs exhibit a 1-nm thick interfacial layer. The internal photoemission measurements indicate that the change in the GaAs polar crystal face orientation from the Ga-terminated (111) A to the As-terminated (111) B has no effect on the barrier height for electrons at GaAs (111)/ALD Al₂O₃ interfaces and remains the same as at the non-polar GaAs (100)/Al₂O₃ interface. Moreover, the presence of native oxide on GaAs (111) or passivation of this surface with sulphur also has no measurable influence on the GaAs (111)/Al₂O₃ barrier. Chou et al.^[40] have indicated that the ALD Al₂O₃ can be chosen as the reference material since the high-mobility semiconductor/Al₂O₃ interfaces represent considerable interest by themselves because ALD Al₂O₃ is widely applied as passivating and insulating layer on A_Ⅲ-B_Ⅴ channels, GaAs (111) A (Ga-terminated) and GaAs (111) B (As-terminated). The cleaning effect of the trimethylaluminum (TMA) precursor allows us to minimize the concentration of sub-oxides at the interface, as has been demonstrated for GaAs. The results^{[34, 40]} suggest that the orientation and composition-sensitive surface dipoles conventionally observed at GaAs surfaces are effectively compensated at GaAs/oxide interfaces. Peng et al.^[41] have shown that electrical bi-direction modification by ferroelectric polarization in LaNiO₃/BaTiO_3-δ heterojunctions, that is, which is realized through the ferroelectric displacement of Ti ions of BaTiO_3-δ polarized downward (upward) to form (break) molecular coupling at the interface, has associated with charge transfer between Ni and Ti that directly causes the resistivity modification of LaNiO₃. They have mentioned that positive voltages would induce charge transfer from Ni to Ti, while negative voltages would induce charge transfer from Ti to Ni, which only causes some accumulation or depletion of carrier at the interface. Again, the findings of Peng et al.^[42] have included the emergence of high-mobility conductivity at the classic LaAlO₃/SrTiO₃ interface due to the interface electronic reconstruction induced by charge transfer between LaAlO₃ and SrTiO₃. Thus, it may be said that the charge transfer between the GaAs/Al₂O₃ may change the space charge in the depletion layer of the MS rectifying contact.

2. Experimental details

The Al₂O₃ interfacial layer was formed on the front surface of the GaAs substrate by atomic layer deposition (ALD) method. The Al₂O₃ thin film was coated using Savannah 100 thermal ALD reactor (Ultratech/Cambridge Nanotech Inc.) at a substrate temperature of 200 ^oC using trimethylaluminum (TMA) and water (H₂O) as aluminum and oxygen precursors, respectively. Exposure time of 0.015 s was used for both precursors while the purge time was adjusted to 10 s. The resulting Al₂O₃ film growth rate was about 1.05 Angstrom per cycle. Standard photolithography technique was used for pattern fabrication on GaAs. Finally the photoresist was removed by washing with DI water and then with N₂. For the Schottky contacts, the n-GaAs wafer was placed on a rotating table. Ti (10 nm) Schottky contacts are made onto Al₂O₃/n-GaAs structure using magnetron DC sputter technique, and Au (50 nm) was evaporated as a top layer onto the Ti/Al₂O₃/n-GaAs structure to protect the Ti metallic layer in high vacuum system of 10^-6 Torr. Ti and Au contacts were squares with 0.01 cm² area. Fig. 1 shows the schematic model of Au/Ti/Al₂O₃/n-GaAs structure. Temperature-dependent measurements were carried out using ARS closed cycle helium cryostat in 20-320 K range. The temperature was stabilized in 50 mK with a LakeShore 330 temperature controller for the I-V and C-V measurements. The voltage for I-V characteristics was applied to sample with 5 mV steps driven from a Keithley 2400, and the current was measured by a Keithley 6514 electrometer. The capacitance was measured by a Boonton 72B capacitance meter under 1 MHz constant frequency.

3. Results and discussion

The surface morphology of the samples was characterized by atomic force microscopy (AFM) of Park Systems-XE100E. Fig. 2 shows AFM surface images with 3D of the GaAs and AFM surface images with 3D of ~ 10 nm thick Al₂O₃ on GaAs substrate. The GaAs surface and the Al₂O₃ layer surface of 10 nm thickness on GaAs are reasonably smooth with root-mean-square (RMS) roughness values of 0.545 and 1.456 nm, respectively.

3.1 Temperature-dependent current-voltage characteristics

The temperature-dependent I-V characteristics for an MIS diode were analyzed by the well-known thermionic emission (TE) equation^{[1, 2, 8-12]}

$I={{I}_{\text{s}}}\left\{ \exp \left[ -\frac{q(V-I{{R}_{\text{s}}})}{kT} \right]-1\text{ } \right\},$

(1)

where the saturation current for a MIS diode is expressed as

${{I}_{\text{s}}}=A{{A}^{*}}{{T}^{2}}\exp \left( -\frac{q{{\Phi }_{\text{b}}}}{kT} \right)\exp \left[ -a\delta {{(\chi )}^{1/2}} \right].$

(2)

Eq. (2) can be arranged as

$kT\ln \frac{A{{A}^{*}}{{T}^{2}}}{{{I}_{\text{s}}}}=q{{\Phi }_{\text{b}}}\text{+}akT{{\chi }^{1/2}}\delta ,$

(3)

and Φ_b is the zero bias effective barrier height (BH) without the interfacial layer, A^* is the effective Richardson constant and equals to 8.16 Acm^-2K^-2 for n-type GaAs, A is Schottky contact area of the diode, T is the absolute temperature, k is Boltzmann constant. The R_s is the series resistance of the neutral region of the semiconductor substrate between the depletion region and ohmic contact in the Schottky diodes. Eq. (2) is identical to standard thermionic emission (TE) equation for Schottky diodes except for the term exp (-aδ (χ)^1/2), which is the tunneling probability^[1-4]. When an interfacial layer is present, the measured zero bias BH qΦ_b0 is given by

$q{{\mathit{\Phi} }_{\text{b}0}}=kT\ln \frac{A{{A}^{*}}{{T}^{2}}}{{{I}_{\text{s}}}},$

(4)

where Φ_b0 =Φ_b0(T) is the zero bias effective BH for an MIS diode at each measurement temperature^[8-12]. From Eqs. (3) and (4), Φ_b0(T) can be written as

$q{{\mathit{\Phi} }_{\text{b}0}}(T)=q{{\Phi }_{\text{b}}}+akT{{\chi }^{1/2}}\delta ,$

(5)

where aδ (χ)^1/2 is the electron tunneling factor, $a=\frac{4\pi }{h}({2m^\ast })^{1/2}$ is a constant depending on effective mass, ${{m}^{*}}=0.067{{m}_{o}}$ is the effective tunneling mass of electrons, χ is the effective BH presented by the thin interfacial layer or the energy difference between the conduction band edge of the semiconductor and that of the interfacial layer, and δ is the thickness of the interfacial layer.

Fig. 3 presents the reverse and forward bias I-V characteristics of the reference Au/Ti/n-GaAs and MIS Au/Ti/Al₂O₃/n-GaAs diodes in the temperature range of 60-300 K with steps of 20 K. The forward bias I-V curves are given in the temperature range of 60-300 K, and the reverse bias I-V curves for MIS diode in the temperature range of 200-300 K with steps of 20 K. As seen from the forward bias I-V curves of both diodes at a given temperature in Fig. 3, the MIS diode has a lower current value than that for the reference diode in a given bias voltage, due to the presence of the Al₂O₃ layer at the metal/GaAs interface. For example, the MIS diode has the current values of $8 \times10^{-9}$ and $3.1 \times 10^{-8}$ A while the reference diode has the current values of $6.1 \times 10^{-6}$ and $3.5~\times~10^{-4}$ A at 0.25 and 0.40 V at 300 K, respectively. The decrease in the current for the MIS diode in respect to the reference diode is supplied from the presence of the Al₂O₃ layer at the metal/GaAs interface because both diodes are made on the GaAs pieces cut from the same wafer. As is well known, when a diode with the interfacial layer is under a bias voltage, a part of the applied voltage drops across the interfacial layer, thus the BH becomes a function of the bias voltage. It can be said that the temperature-dependent I-V characteristics of the MIS diode do not obey the thermionic emission current theory. This discrepancy can be attributed to the Al₂O₃ interfacial layer. The interface trap charges located at the Al₂O₃-GaAs interface, with energy states in the semiconductor forbidden bandgap cause deviation of the forward-bias I-V characteristics from the ideal behavior. In addition, Fowler-Nordheim direct tunneling at higher voltages in the forward-bias direction may be the responsible and dominant mechanism for lowering current in the MIS diode^{[1-4, 14]}. Furthermore, as can be seen from the reverse bias I-V curves of the MIS diode in Fig. 3, the presence of the interfacial layer is a cause of the soft (non-saturation) behavior of the reverse bias I-V curves depending on the bias voltage, because of the reduction in the BH with increasing reverse bias voltage^[1-16]. Schottky emission at the dielectric/GaAs interface at high electric fields, and Poole-Frenkel emission at high temperatures due to traps present in the bulk of the dielectric may be said to be responsible for the soft (non-saturation) behavior in reverse bias. The origin of these traps in this case has been widely reported to be donor-like traps within the ALD Al₂O₃ layer, most likely oxygen vacancies^{[1-4, 14]}.

The case can clearly be seen from Fig. 4. Following Ref.[56], the diffusion potential V (0, z) along the z axis and at the center of the low-barrier, circular patch with the effective patch radius R₀ can be expressed as^[56]:

$V(0,z)={{V}_{\text{b}}}{{\left( 1-\frac{z}{W} \right)}^{2}}+{{V}_{\text{n}}}+V-\Delta \mathit{\Phi} \left[ 1-\frac{z}{{{\left( {{z}^{2}}+R_{0}^{2} \right)}^{1/2}}} \right],$

(6)

where V_b = Φ_hom-V_n-V is the band bending due to the metal-semiconductor contact with a uniform BH Φ_hom, V_n is the potential difference between Fermi level and the conduction band edge in the neutral region, V is the applied voltage, △Φ is the difference between the uniform BH Φ_hom and the low BH, W is the depletion width defined as ${{\left( 2{{\varepsilon }_{0}}{{\varepsilon }_{\text{s}}}{{V}_{\text{b}}}/q{{N}_{\text{d}}} \right)}^{1/2}}$ where ${{\varepsilon }_{\text{s}}}$ and ${{\varepsilon }_{\text{O}}}$ are the dielectric constant of the semiconductor and free space, respectively, q the electronic charge. Fig. 4 shows the diffusion potential variations for low-BH circular patches under the bias voltage, from the reverse bias of-0.30 V to forward bias of 0.30 V with the steps of 0.10 V, as a function of the distance z from the MS interface toward the semiconductor. Note that the saddle-point potential rises with forward bias and decreases with reverse bias, leading to unsaturated reverse current^[43-56]. These curves are plotted using Eq. (6) above. Moreover, the bias dependence of the BH changes the shape of the I-V curves because the BH increases (decreases) with increasing forward bias (reverse bias) voltage in a given temperature. As mentioned in Refs. [56, 66], the potential barrier between the semiconductor and metal does not depend on temperature, but it increases with forward bias and decreases with the reverse bias, as can be seen from Fig. 4^[56-58]. The dependence of the potential on applied bias is the key to understanding a number of abnormal events in I-V measurements. Thus, the barrier change at low temperatures may be ascribed to the current flow through the small regions so-called patches with low BH^[54-60].

As can be seen from Eq. (1), the current flow across the device is proportional to the bias voltage V, and is inversely proportional to temperature. Fig. 5 shows the experimental current versus $(kT)^{-1}$ curves with the forward bias as a parameter for the MIS structure, in the temperature range of 60-300 K. The curves in the figure are plotted from the I-V-T data of the MIS diode in Fig. 3 to analyze the dependence of the current flow on the bias and temperature. In the MIS structure, the TE across Au/Ti/Al₂O₃ interface or Al₂O₃/n-GaAs interface is responsible for the charge transport. Tunnel emission is independent of the measurement temperature but has the strongest dependence on the applied voltage. That is, each process may dominate at given temperature and bias voltage range. The processes are not independent of one another. As seen from Fig. 5, the current flow is essentially independent of the measurement temperature at high bias voltages and low temperatures that Schottky emission dominates. The tunneling caused by the emission of the trapped electrons into the conduction band dominates at high bias voltages and low temperatures, as can be seen from the experimental current versus $({kT})^{-1}$ curves (Fig. 5). The contribution of the ohmic compound to current dominates at low bias voltages and moderate temperatures^[1-5].

The forward bias I-V curves of the MIS structure do not have only a single straight line or one linear region over the whole forward bias voltage, as can be seen from Fig. 3. The number of the regions with straight line in the forward bias I-V curves increases with decreasing temperature. For example, there are two regions in each I-V curve from 220 down to 300 K while there are three regions in each I-V curve from 60 to 200 K, as can be seen from Fig. 6 (for 180 K) and Fig. 7 (for 300 K). That is, the I-V curves at temperatures above 200 K have two regions, one of these regions is called Ⅰ. region at low voltages, and the other is called Ⅲ. region at high voltages, as seen from Figs. 6 or 7. In the I-V curves at temperatures below 220 K, a new region called Ⅱ. region at moderate forward biases appears between Ⅰ. and Ⅲ. region. The current range for each I-V curve of Ⅱ. region expands with decreasing temperature. It can be suggested that the barrier inhomogeneities can occur as a result of inhomogeneity of the barrier height and the non-uniformity of the interfacial charges^{[3, 64-73]}. As explained by Tung^[58], when the interface BH is non-uniform, the current transport across the MS interface is spatially inhomogeneous. The device current exponentially depends on the BH and the low BH patches are the more pronounced at low measurement temperatures and low bias voltages^[56-68]. The series resistance becomes important in the case where the current at low barrier patch is higher than the current at the uniform regions, at the low temperature I-V characteristics. The I-V curve shows a double or more slope. In such a case, ohmic effect may be significant even at moderate forward bias. This is the reason for the double slope or triple slope in the forward bias I-V characteristics^[63-78].

Figs. 6 and 7 show the experimental forward-bias current-voltage curves and their fits in each region for the MIS structure at 180 and 300 K, respectively. In Figs. 6 and 7, the symbols represent the actual experimental data, and the dashed curves are theoretical fittings based on the well-known thermionic emission Eq. (1). It should be mentioned that ideality factor much larger than 1.1 shows that the transport properties of the device are not well modeled by TE only. Thus the BH is merely a curve fitting parameter for these samples and should not be interpreted as representing the true BH^[53-66]. The dashed I-V curves in Fig. 6 (180 K) and Fig. 7 (300 K) are fits to the experimental data using Φ_b0, n and the series resistance $R_{s}$ as adjustable parameters by Eq. (1). For 180 K in Fig. 6, the calculations were realized using Φ _b0 = 0.556 eV, n=4.5, ${{R}_{\text{s}}}=3.5\times {{10}^{4}}\ \text{k}\Omega$ and $A=1\times {{10}^{-2}}$ cm² for Ⅰ. region, and Φ_b0 = 0.59 eV, n=3.78 and ${{R}_{\text{s}}}=2.0\times {{10}^{3}}\ \text{k}\Omega$ for Ⅱ. region, and Φ_b0= 0.635 eV, n=3.45 and ${{R}_{\text{s}}}\text{=16}\text{.5 k}\Omega$ for Ⅲ. region. For 300 K in Fig. 7, Φ_b0= 0.775 eV, n=4.0, ${{R}_{\text{s}}}\text{=16}\text{.5 k}\Omega$ and $A=10^{-2}$ cm² for the small-bias Ⅰ. region, and Φ_b0= 0.848 eV, n=3.43 and ${{R}_{\text{s}}}\text{= 3}\text{.85 k}\Omega$ for the high-bias Ⅲ. region. As mentioned above, the current will preferentially flow through the few barriers with the lowest BH and may be orders of magnitude higher than the average current density, and thus, local resistance effects become more dominant. In such a case, the ohmic effect may be significant even at moderate forward bias^[53-76]. As can be seen from the values of the diode parameters above, the lower-BH patches are dominant at the lower measurement temperatures and the small bias voltages, and the ideality factor is larger than unity^[53-72]. That is, the presence of the oxide layer^{[1-12, 68-72]} and the SBH inhomogeneity^[53-72] may alter the shape of I-V plots. As can be seen from Figs. 6 and 7, the current flow through a low SBH patch is characterized by an ideality factor greater than unity. At high temperatures, the ideality factor is close to unity and bias voltage and the current flow is less dominated by the small number of low-SBH regions and the current flow through the uniform region accounts for most of the total current ^{[29-41, 72-89]}.

In spite of these, when considering the forward bias I-V curves of the reference Au/Ti/n-GaAs diode without interfacial layer, the I-V curve of the reference diode at each temperature extends linearly until the series resistance region at high bias voltage, in contrast to those of the MIS structure. Furthermore, the BH value from the temperature-dependent forward bias I-V curves of the reference diode has increased from 0.77 eV at 300 K to 0.81 eV at 180 K, and has approximately remained in the value of 0.81 eV from 130 to 180 K, and then has sharply decreased from 0.81 eV at 130 to 0.48 eV at 60 K because the current preferentially flows through the lowest BH with decreasing temperature due to the barrier height inhomogeneity. The measured ideality factor value of the reference device has remained almost unchanged from 1.07 at 150 to 1.10 at 300 K, and has decreased from 1.10 at 150 K to 1.22 eV at 60 K. When considering barrier height values for both diodes, it may be said that the reduction in forward current of the MIS Au/Ti/Al₂O₃/n-GaAs diode in relation to that of the reference Au/Ti/n-GaAs diode is due to the concurrence of an increase in barrier height.

Fig. 8 shows the experimental forward bias BH versus measurement temperature curves for the MIS structure. It can be seen from Fig. 8 that the BH versus temperature curve for the Ⅰ. region and Ⅲ. region changes with the linear, the BH curves for these two regions are formed from the straight lines in parallel with each other. The fits to the straight lines in Fig. 8 give the expressions Φ1_b0(T) = (0.00184T + 0.23) eV for Ⅰ. region and Φ3_b0 (T) = (0.00178T + 0.31) eV for Ⅲ. region. Then, the slope values of 0.00184 eV/K and 0.00178 eV/K of the straight lines for Ⅰ. region and Ⅲ. region in Fig. 8, respectively, correspond to aδχ^1/2 in Eq. (5), where Boltzmann constant k equals $8.625 \times 10^{-5}$ eV/K, δ=100 Å and the quantity a equals 0.265 eV^-1/2Å^{-1 [5, 11]}. Thus, an average value of 20.64 is found for the electron tunneling factor, aδχ^1/2, in the presence of the Al₂O₃ layer. Thus, an average value of χ = 0.627 eV was obtained for the mean tunneling BH presented by the Al₂O₃ layer. As is well known, the BH presented by insulating layer, χ, is distinct from the zero bias BH Φ_b0 which is expressed as the maximum height of the bottom of conduction band edge of the semiconductor relative to the metal Fermi level on the semiconductor surface. It has been reported a value of about 0.63 eV for χ from the I-V measurements in 98-298 K range stepped by 25 K, for Au/Polypyrrole/n-InP Schottky diodes^[81], and Biber et al.^[82] have obtained a value of χ =0.33 eV from the I-V curves of Au/oxide layer/n-GaAs MIS diodes formed by the anodic oxidation method, their I-V measurements have been made in 80-300 K range with the steps of 20 K^[82]. The IPE (internal photoemission) measurements reveal that the electron BH between the top of the GaAs valance band (VB) and the bottom of the Al₂O₃ conduction band (CB) shows no measurable variation when changing the surface orientation of the GaAs substrate crystal and its chemical treatment prior to Al₂O₃ deposition. This result suggests that the surface dipoles at the free GaAs surfaces known from previous studies are largely compensated by charge transfer between atoms in the oxide layer^[34].

3.2 Temperature-dependent capacitance-voltage characteristics

The capacitance, C, per area unit of a Schottky diode is given by^[1-4]

$C={{\left[ \frac{q{{N}_{\text{D}}}{{\varepsilon }_{\text{s}}}{{\varepsilon }_{0}}\text{ }}{2\left( {{V}_{\text{D}0}}-V-kT \right)} \right]}^{1/2}},$

(7)

or

$C=\left[ \frac{q{{N}_{\text{D}}}{{\varepsilon }_{\text{s}}}{{\varepsilon }_{0}}}{2\left( {{V}_{\text{D}0}}-V-kT \right)} \right]{{\text{ }}^{1/2}},$

(8)

where q is the electron charge, N_D is the doping concentration of the n-type semiconductor, ε_s and ε_o are the permittivity of the semiconductor and free space, respectively, V_D0= (Φ_b0-V_n) is the diffusion potential at zero bias, Φ_b0 is the zero bias Schottky BH, V_n is the potential difference between Fermi level and the conduction band edge in the neutral region, V is the applied voltage.

Fig. 9 shows the temperature-dependent capacitance (C-T) curves for the reference and MIS structures at 1.0 MHz and various bias voltages. The capacitance value of the MIS diode is larger than that of the reference diode at a given temperature for every bias voltage. The observed discrepancies can be attributed to an increase of the space charges in the depletion region due to the presence of the Al₂O₃ interface layer as both the MIS and reference diodes have been made on GaAs cut from the same wafer. As can be seen from Fig. 9, for both diodes, the capacitance value remained almost unchanged from 60 to 120 K at each bias voltage, which can be attributed to the freeze-out of carriers at low temperatures, as will be seen from Fig.9. From 120 to 300 K, the capacitance value for the diodes increases with increasing temperature at each bias voltage. But, the capacitance for the MIS diode increased a greater slope as compared with the reference diode, from 220 to 300 K.

Figs. 10 and 11 shows the C^-2-V plots for the reference and MIS structures at some temperatures and 1.0 MHz, respectively. Two straight line regions have been observed from +0.20 to-2.0 V in the C^-2-V curves at higher temperatures, as can be seen from the figures. The two regions are mostly reduced to one region over the whole bias voltage (+0.20 to-2.0 V) at temperatures below 220 K. The free carrier concentration of the n-type GaAs substrate can be calculated using the slope values of the C^-2-V curves of the MIS diode in Eq. (8). The region corresponding to (-0.7 V)-(-2.0 V) range in the C^-2-V curves at each temperature was called Ⅰ. CV region, and the region corresponding to (-0.7 V)-(+0.2 V) range was called Ⅱ. CV region. The experimental barrier height, free carrier concentration and V_n values for the reference Au/Ti/n-GaAs and MIS Au/Ti/Al₂O₃/n-GaAs structures were calculated from C^-2-V characteristics in Figs. 10 and 11 for each temperature. The BH and V_n values for the Ⅱ. CV region are only given in Table 1.

Fig. 12 shows the temperature-dependent carrier concentrations from C^-2-V plots for the reference and MIS structures at 1.0 MHz. As can be seen from Fig. 12, the free carrier concentration of the MIS diode is larger than that of the reference diode at temperatures above 120 K. The carrier concentration N_D for the n-type GaAs under study was given as $7.43 \times 10^{15}$ cm^-3 by the manufacturer for a temperature of 300 K^{[15, 16]}. The values of about $6.8 \times 10^{15}$ cm^-3 and $7.48~\times~10^{15}$ cm^-3 for the reference diode were obtained from the Ⅰ. CV region for the C^-2-V curves at 280 and 300 K (Fig.10), respectively. It is clearly seen that the value of $7.48 \times 10^{15}$ cm^-3 almost is the same as the value of $7.43 \times 10^{15}$ cm^-3 given by the manufacturer within the experimental errors. Therefore, it can be said that the N_D value from Ⅰ. CV region corresponds to that of the reference diode. A value of $4.53 \times 10^{15}$ cm^-3 for the reference diode was obtained from the Ⅱ. CV region at 300 K. As can be seen, the value of $4.53 \times 10^{15}$ cm^-3 at 300 K has a reduction of 40% from value of $7.43 \times 10^{15}$ cm^-3 given by the manufacturer. The presence of positive or negative interface state charges in equilibrium with semiconductor affects the space charges in the depletion layer of the semiconductor^[1-4]. It has been reported that some defects in GaAs were introduced by the DC magnetron sputtered deposition technique^[18]. These defects maybe caused the formation of the defect-induced interface states within the band gap of the semiconductor at metal-semiconductor interface. Therefore, a reduction of 40% in the doping concentration obtained from the Ⅱ. CV region at 300 K or in the positive space charges in the depletion region of metal/n-type semiconductor Schottky contact shows the presence of negatively charged interface acceptors in the interface states which are in equilibrium with semiconductor substrate^[1-13]. Another explanation has been made by Peng et al.^{[41, 42]} for LaAlO₃SrTiO₃ and LaNiO₃BaTiO_3-δ interfaces. They^{[41, 42]} have mentioned that the interface electronic reconstruction induced by charge transfer between LaAlO₃ and SrTiO₃ or LaNiO₃ and BaTiO_3-δ causes some accumulation or depletion carrier change at the interface. Thereby, it may be said that the charge transfer between the GaAs and Al₂O₃ may cause the change of the positive space charge concentration in the depletion region of the Au/Ti/Al₂O₃/n-GaAs structure.

The values of approximately $1.41 \times 10^{16}$ cm^-3 and $1.51 \times 10^{16}$ cm^-3 for the MIS diode were obtained from the Ⅰ. CV region of the C^-2-V curves at 280 and 300 K (Fig. 11), respectively. The average carrier concentration found for the MIS structure is twice as large as that of the reference diode or that given by the manufacturer. The values of about $6.94 \times 10^{15}$ and $9.67 \times 10^{15}$ cm^-3 for the MIS diode were obtained from the Ⅰ. CV region for temperature of 280 and 300 K, Fig. 11, respectively. As can be seen, the value of $9.67 \times 10^{15}$ cm^-3 at 300 K has an increase of 30 percent from value of $7.43 \times 10^{15}$ cm^-3 given by the manufacturer. As mentioned above, such an appreciable difference in the doping concentration from each of the two regions for the MIS diode with the Al₂O₃ interfacial layer cannot be attributed to doping variations in the semiconductor bulk because both diodes were made on pieces cut from the same n-type GaAs wafer. The increase in the doping concentration may be ascribed to the presence of interface charges in the interface states which are in equilibrium with semiconductor substrate and which causes the change of the positive space charge concentration in the depletion region of the device, because of the presence of the Al₂O₃/n-GaAs interface^[1-13], or may be ascribed to the charge transfer between the GaAs/Al₂O₃ interface^{[26, 34, 38-42]}.

4. Conclusion

The I-V and C-V characteristics of Au/Ti/n-GaAs with and without the Al₂O₃ interfacial layer have been measured in the temperature range of 60-300 K. A high carrier concentration for the MIS structure has been obtained more than that for the reference structure. Such a difference in the doping concentration has been attributed not to doping variation in the semiconductor bulk but to the presence of the Al₂O₃ interfacial layer, and to the charge transfer between the GaAs (111)/Al₂O₃ interface. It has been seen that the temperature-dependent I-V characteristics of the reference diode obey the TE current theory at high temperatures. The I-V characteristics deviate off the ideality at low temperatures because the current will preferably flow through the lowest BH. The presence of the Al₂O₃ layer in the MIS diode changes the shape of the I-V curves compared to those of the reference diode. A value of 20.64 is found for the electron tunneling factor, aδχ^1/2, from the temperature-dependent I-V characteristics of the MIS structure. Thus, an average value of 0.627 eV for the mean tunneling BH presented by the Al₂O₃ layer, χ, has been calculated from the experimental I-V-T data.