1. Introduction

The low temperature poly-Si thin film transistor (LTPS TFT) is an excellent candidate for realizing high performance active matrix liquid crystalline display (AMLCD) or organic light emitting diode display (AMOLED) ^{[1, 2]}. Compared with hydrogenated amorphous silicon (a-Si:H) TFT or metal-oxide (MO) TFTs, LTPS TFT possesses many merits, such as high mobility and good stability over long operating time with voltage or current stressing^{[3, 4]}. In particular, p-type LTPS TFTs are widely used as the stability of p-type transistor is better than that of n-type transistor^[5]. In addition, gate driver and de-mux circuits can also be implemented using LTPS TFTs for simplification of the manufacturing process^{[6, 7]}. Integration of the gate driver is critical for narrow bezel display panel, as the number of external ICs and its related connections can be reduced, and also module process can be greatly simplified^{[8, 9]}.

However, an integrated gate driver cannot be implemented using conventional CMOS circuit topology with only p-type LTPS TFTs. Several new gate driver schematics employing bootstrapping methods were proposed previously^[10-17]. Ha et al. proposed an integrated gate driver using multiple clock signals (CKs)^[10]. Although structure of the circuit seems quite simple as only 6 TFTs are required for every single stage, clock bus lines occupy too much of the layout areas. What is more, numbers of external level-shifter ICs will be increased. Han et al. proposed that a gate driver can also be implemented using only two clock signals and a doublebootstrapping scheme was illustrated^[12]. But the number of TFTs of single stage is increased which hinders the narrowing of display bezel.

This paper presents a new simple p-type LTPS TFTs integrated gate driver circuit with two non-overlapped clocks. For the single gate driver stage, only six TFTs and one capacitor are used. The influence of TFTs' size and capacitance on transient performance of the proposed gate driver is thoroughly investigated.

2. Proposed circuit and operations

Fig. 1 shows a schematic of a conventional gate driver with single stage^[18], which consists of 10 TFTs and 1 capacitor. Fig. 1(b) illustrates the simulated waveforms. It is observed that, although low level pulses of OUT[n] can be generated following that of IN, unexpected pulses appear at the initialization period of frame time. For the initialization period, many TFTs are cut off, such an T1, T2 and other TFTs which are signed with 'X'. Thus, T5 and T6 are both in the high impedance state as the gate electrode of T5 (i.e. node Q) and T6 (i.e. node P) is uncertain. Therefore, OUT[n] is determined by equivalent resistant of T5 and T6 and it cannot be maintained at V_H. Unfortunately, the distortion in OUT[n] is prone to lead to false operation of the following gate driver stages.

Fig. 2 shows a schematic of the proposed gate driver with block diagram, and single-stage circuit, and the timing diagram. Single stage of the proposed gate driver consists of input part, driving part, discharging part, and high-level-holding part. The input part includes T3, which connects the input terminal and gate electrode of T1 (i.e. node Q). The driving part includes T1 and C1, which pulls-up/down output terminal by the bootstrapping method, while the discharging part includes T2 and voltage of node Q is pulled down by charge sharing between node Q and output terminal. The high-level-holding part includes T4, T5 and T6. In addition, IN is the input signal, and V_H/V_L represent the high/low voltage level of the CKs/IN. OUT is the output terminal, which is connected with gate lines of TFT panel. For simplicity of analysis, gate lines of TFT panel can be modeled by serially connecting R_L and C_L.

The timing diagram is shown in Fig. 2 (c), and circuit operations are detailed as follows.

2.1 Initialization period (P1)

In the P1 phase, T3 is turned off as the voltage level of IN is V_H. When CK1 switches to V_L, T2 and T4 are turned on. Thus T5 is also turned on as node P is pulled down to V_L. Consequently, node Q and OUT[n] are connected through T2 and they are both charged up to GND through T5. Otherwise, if CK1 is at the level of V_H, node Q and OUT[n] maintain the level of GND. For the initialization period, whether CK1 is V_H or V_L, T1 can be well turned off, and the level of node Q and OUT[n] are maintaining the level of GND. In other words, the unexpected pulses during the initialization phase can be avoided for the proposed schematic.

2.2 Pre-charge period (P2)

In the P2 phase, T2 and T4 are turned off as their gate electrodes are biased with V_H. T3 is turned on as the level of IN is V_L. Thus node Q is pulled down to V_L-V_TH3 where V_TH3 denotes the threshold voltage of T3. Hence, T1 and T6 are turned on. As a result, T5 is turned off as node P is pulled up to V_H through T6. For P2 phase, OUT[n] maintains the level of V_H as OUT[n] is connected with CK1 through T1.

2.3 Bootstrapping period (P3)

In the following P3 phase, T1 and T6 are still kept on as voltage of their gate electrodes (node Q) remains low. As CK1 switches to V_L, OUT[n] can be pulled down to V_L through T1. The charges accumulated during the pre-charge period are re-distributed between the capacitance associated with node Q, namely T1's gate-to-source capacitance (C_GS1), gate-to-drain capacitance (C_GD1), and C₁. As Q node is nearly floating, according to the charge conservation law, voltage of Q node is bootstrapped to (V_L-V_TH3)+(V_L-V_H). It seems that T2 is turned on during P3 period as its gate electrode is biased with V_L. However, due to the bootstrapping effect, the voltage of T2's source (i.e. OUT[n]) is pulled-down to V_L in a short time, and the voltage of T2's drain (i.e. Q) is decreased to (V_L-V_TH3)+(V_L-V_H), so T2 can be turned off as V_GS2 equals 0, which is larger than V_TH2. Although there might be leakage current through T2 during the transient time, as falling time of OUT[n] is relatively short, it is reasonable to assume that Q node is floating. In addition, because both T4 and T6 are turned on, voltage of node P depends on the voltage distribution between T4 and T6. Since T4 operates in the saturation region, the conduction current of T4 can be expressed as

${{I}_{\text{T4}}}=\frac{1}{2}{{\mu }_{\text{n}}}{{C}_{\text{OX}}}\frac{{{W}_{\text{T4}}}}{L}{{({{V}_{\text{L}}}-{{V}_{\text{P}}}-{{V}_{\text{TH4}}})}^{2}},$

(1)

where μ_n, C_OX are the mobility and gate capacitance per unit area, respectively, and W_T4 and L are width and length of T4, respectively.

For T6, as it operates in the linear region, the conduction current of T6 can be expressed as

${{I}_{T6}}={{\mu }_{\text{n}}}{{C}_{\text{OX}}}\frac{{{W}_{\text{T}6}}}{L}[({{V}_{\text{Q}}}-{{V}_{\text{TH}6}})(-{{V}_{\text{P}}})-\frac{1}{2}{{V}_{\text{P}}}^{2}],$

(2)

where W_T6 represents width of T6. As T4 and T6 are serially connected, their currents are equaled, and it can be derived that

$\begin{align} &-\frac{1}{2}{{\mu }_{\text{n}}}{{C}_{\text{OX}}}\frac{{{W}_{\text{T4}}}}{L}{{({{V}_{\text{L}}}-{{V}_{\text{P}}}-{{V}_{\text{TH4}}})}^{2}} \\ &={{\mu }_{\text{n}}}{{C}_{\text{OX}}}\frac{{{W}_{\text{T6}}}}{L}[({{V}_{\text{Q}}}-{{V}_{\text{TH6}}})(-{{V}_{\text{P}}})-\frac{1}{2}{{V}_{\text{P}}}^{2}]. \\ \end{align}$

(3)

As both T4 and T6 are switching transistors, their width is usually chosen the same. Thus, it is convenient to derive that

${{V}_{\text{P}}}=\frac{1}{6}({{V}_{\text{L}}}-{{V}_{\text{TH4}}}).$

(4)

As the voltage of T5's source (i.e. OUT[n]) is pulled-down to V_L, T5 is turned off as V_GS5 equals V_P =$\frac{1}{6}$(V_L-V_TH4), which is larger than V_TH5.

When CK1 switches to V_H, T2, T3 and T4 are turned off. Thus Q node is still floating. Although voltage of Q node is positively coupled to V_L-V_TH3 due to feed through effect, T1 is still turned on. Thus OUT[n] can be pulled up to V_H through T1. In addition, Node P is charged up to GND through T6. So T5 has no contribution to pulling-up of OUT[n], and T1 takes the role of both pulling-down and pulling-up of OUT[n] to save layout areas.

2.4 Charge-sharing period (P4)

In the P4 phase, when CK1 switches to V_L, T2 is turned on. Consequently, Q node and OUT[n] are connected together through T2, and voltage of Q node depends on the charge-sharing effect between capacitance of gate line (C_L) and Q node (C₁). The charge stored on the capacitor C₁ during the pre-charge and bootstrapping period is approximately

${{Q}_{1}}={{C}_{1}}({{V}_{\text{L}}}-{{V}_{\text{TH3}}}).$

(5)

After pulling-up period, voltage of C_L is ground, thus charge stored on C_L is

${{Q}_{2}}=0.$

(6)

Thus, due to charge-sharing effect, voltage of node Q can be expressed as

${{V}_{\text{Q}}}=\frac{{{C}_{1}}({{V}_{\text{L}}}-{{V}_{\text{TH3}}})}{{{C}_{1}}+{{C}_{\text{L}}}}.$

(7)

As C_L is much greater than C₁, by the end of charge-sharing period, V_Q can be pulled up to ground level approximately. Consequently, T1 can be turned off in a relatively short time. In addition, voltage of node P can be pulled down to V_L-V_TH4 as T4 is turned on. Thus T5 is turned on and OUT[n] can be maintained at ground level through T5.

2.5 High-level holding period (P5)

In the P5 phase, when CK1 switches to V_L, T2, T4 and T5 are turned on. Thus node Q and OUT[n] are still connected through T2. Consequently, both node Q and OUT[n] can be maintained at V_H and T1 is turned off. On the other hand, when CK1 switches to V_H, although T2 and T4 are turned off, T5 can still be kept on as voltage of node P maintains the low level by gate capacitance of T5. Thus voltage of OUT[n] is connected with GND through T5. The voltage of Q can also be kept by GND due to capacitances associated with node Q. To sum up, whether CK1 is V_H or V_L, both node Q and OUT[n] are kept at V_H for P5 period, and clock feed-through effects can be avoided^[19].

3. Results and discussions

Simulations using SmartSpice are carried out for the verification of the proposed gate circuit. RPI model with level 36 is used for LTPS TFT characteristic modeling and parameters are adjusted correspondingly. Fig. 3 shows the comparison of simulated current-voltage (I-V) and that of the experimental results. The dots and lines represent the measured and simulated results, respectively. The simulated results are a good match with the measured ones.

Table 1 shows the extracted parameters for LTPS TFTs. The threshold voltage and mobility are extracted using the linear-interception method. Here, gate capacitance per unit area (C_OX) is estimated to be 34.5 nF/cm².

Table 2 shows the device parameters of the proposed gate driver. The clock pluses have an amplitude of 15 V, with high level V_H = 0 V and low level V_L =-15 V. The bootstrap capacitance C₁ and the load capacitance C_L are 0.8 and 300~pF, respectively. In addition, the load resistance is 2000 Ω.

Fig. 4 shows the simulation results of the proposed circuit. The falling and rising time of OUT[1] is 1.69 and 2.28 μs, respectively. Voltage of node P can be kept low, and noise voltage during the initialization phase can be suppressed. The aforementioned operating mechanism of the gate driver is well verified by the simulation results. It is also observed that there is waveform burr of node Q by the rising and falling edge of CK1 due to feedthrough effects associated with the C_GS1. As previously mentioned, the coupled charges at node Q can be discharged through T2 and T5, thus these waveform burrs last a rather short time. Therefore node Q can still be maintained at V_H.

Fig. 5 shows the waveforms of OUT[1], OUT[3], OUT[98] and OUT[100] for the proposed circuit. The pulse width of the CKs is reduced to 5 μs. The proposed gate driver can still correctly generate the sequential scanning signals for gate lines, which might be used in high resolution display applications.

Fig. 6 shows the waveforms of the proposed gate driver with different C₁. In the case of C₁ equaling 0.2 and 0.5 pF, scanning pulse in OUT[n] disappears and the gate driver malfunctions. Bootstrapping operations can only be guaranteed if C₁ is increased to be larger than 0.8 pF. This is in close relationship with the turning-on interval for T2 during the bootstrapping phase. As mentioned before, there is positive feedback with the falling of OUT[n] and turning-off of T2. If C₁ is too small, the charges stored at node Q can easily be leaked through T2 and T1 will be turned off instead of being active for pulling-down/up of OUT[n]. It seems that C₁ should be as large as possible for enhancing the bootstrapping effects. However, layout areas will be increased unexpectedly with too much C₁. Consequently, trade-offs should be made between the transient performance and layout areas for the choice of C₁.

Fig. 7(a) shows the evolution of falling/rising time of OUT[n] versus different V_TH. It is observed that, the falling/rising times are increased with the increase of V_TH. This seems controversial as increasing of threshold voltage should result in increasing of T1's conductivity, which should help decreasing of rising and falling time. The explanations are provided as follows. The equivalent resistance of T1 can be approximately expressed as

${{R}_{\text{eq}}}=\frac{1}{{{\mu }_{\text{n}}}{{C}_{\text{OX}}}\frac{{{W}_{\text{T1}}}}{L}({{V}_{\text{SG1}}}+{{V}_{\text{TH1}}})}.$

(8)

The rising and falling time can be derived as

$t=2.2{{R}_{\text{eq}}}{{C}_{\text{L}}}.$

(9)

Due to the increase of T2's threshold voltage, there is increased charge leakage through T2 during the bootstrapping periods. Fig. 7(b) demonstrates the transient response of V_Q with different V_TH. It is proven that bootstrapping effects are deteriorated due to increased charge loss. Thus V_SG1 will be decreased, and equivalent resistance of T1 will be increased according to Eq. (8). Consequently, rising and falling time will be increased according to Eq. (9).

4. Conclusion

In this paper, a new LTPS TFTs gate driver circuit with charge-sharing structure is proposed. Only one buffer TFT is used for pulling-down/pulling-up of gate scan line for the gate driver unit. Investigations show that voltage bootrapping can be maintained once C₁ is larger than 0.8 pF. The proposed gate driver can still function properly with positive V_TH shift within 0.4 V and negative V_TH shift within-1.2 V. The pulse of gate driver outputs can be reduced to 5 μs. Therefore the proposed gate driver is robust and suitable for high resolution display.